The low-field electron mobility in rectangular silicon nanowire (SiNW) transistors was computed using a self-consistent Poisson-Schrödinger-Monte Carlo solver. The behavior of the phonon-limited and surface-roughness-limited components of the mobility was investigated by decreasing the wire width from 30 nm to 8 nm, the width range capturing a crossover between two-dimensional (2D) and one-dimensional (1D) electron transport. The phonon-limited mobility, which characterizes transport at low and moderate transverse fields, is found to decrease with decreasing wire width due to an increase in the electron-phonon wavefunction overlap. In contrast, the mobility at very high transverse fields, which is limited by surface roughness scattering, increases with decreasing wire width due to volume inversion. The importance of acoustic phonon confinement is also discussed briefly.
We study the low-temperature electron mobility of InSb nanowires. We extract the mobility at 4.2 Kelvin by means of field effect transport measurements using a model consisting of a nanowire-transistor with contact resistances. This model enables an accurate extraction of device parameters, thereby allowing for a systematic study of the nanowire mobility. We identify factors affecting the mobility, and after optimization obtain a field effect mobility of $\sim2.5\mathbin{\times}10^4$ cm$^2$/Vs. We further demonstrate the reproducibility of these mobility values which are among the highest repo…
Electronic band structure and energetic stability of two types of and oriented silicon nanowires in beta-Sn phase with the surface terminated by hydrogen atoms were studied using density functional theory. It was found that beta-Sn nanowires are metastable with zero band gap against to alpha-diamond nanowires. The relative energy of the studied wires tends to the energy of the bulk silicon crystal in beta-Sn phase.
We study by means of density-functional calculations the role of lateral surface reconstructions in determining the electrical properties of <100> silicon nanowires. The different lateral reconstructions are explored by relaxing all the nanowires with crystalline bulk silicon structure and all possible ideal facets that correspond to an average diameter of 1.5 nm. We show that the reconstruction induces the formation of ubiquitous surface states that turn the wires into semi-metallic or metallic.
The dielectric environment of thin semiconductor nanowires can affect the charge transport properties inside the wire. In this work, it is shown that Coulomb impurity scattering inside thin nanowires can be damped strongly by coating the wire with a high-k dielectric. This will lead to an increase in the mobility of free charges inside the wire.
Silicon nanowires are prepared by the method of the two-step metal-assisted wet chemical etching. We have analyzed the structure of solid, rough and porous nanowire surfaces of boron-doped silicon substrates with resistivities of ρ> 1000 Ωcm, ρ= 14-23 Ωcm, ρ< 0.01 Ωcm by scanning electron microscopy and nitrogen gas adsorption. Silicon nanowires prepared from highly-doped silicon reveal mesopores on their surface. However, we found a limit for pore formation. Pores were only formed by etching below a critical H$_2$O$_2$ concentration (c$_{\mbox{H}_2\mbox{O}_2}$ < 0.3 M). Furthermore, we have d…
We report on the heterogeneous nucleation of catalyst-free InAs nanowires on Si (111) substrates by chemical beam epitaxy. We show that nanowire nucleation is enhanced by sputtering the silicon substrate with energetic particles. We argue that particle bombardment introduces lattice defects on the silicon surface that serve as preferential nucleation sites. The formation of these nucleation sites can be controlled by the sputtering parameters, allowing the control of nanowire density in a wide range. Nanowire nucleation is accompanied by unwanted parasitic islands, but by careful choice of ann…
Silicon nanowires grown along the <100>-direction with a bulk Si core are studied with density functional calculations. Two surface reconstructions prevail after exploration of a large fraction of the phase space of nanowire reconstructions. Despite their energetical equivalence, one of the reconstructions is found to be strongly metallic while the other one is semi-metallic. This electronic-structure behavior is dictated by the particular surface states of each reconstruction. These results imply that doping is not required in order to obtain good conducting Si nanowires.
We report low-temperature electrical transport studies of molecule-scale silicon nanowires. Individual nanowires exhibit well-defined Coulomb blockade oscillations characteristic of charge addition to a single nanostructure with length scales up to at least 400 nm. Further studies demonstrate coherent charge transport through discrete single particle quantum levels extending the whole device, and show that the ground state spin configuration follows the Lieb-Mattis theorem. In addition, depletion of the nanowires suggests that phase coherent single-dot characteristics are accessible in a regim…
The giant piezoresistance (PZR) previously reported in silicon nanowires is experimentally investigated in a large number of surface depleted silicon nano- and micro-structures. The resistance is shown to vary strongly with time due to electron and hole trapping at the sample surfaces. Importantly, this time varying resistance manifests itself as an apparent giant PZR identical to that reported elsewhere. By modulating the applied stress in time, the true PZR of the structures is found to be comparable with that of bulk silicon.
The atomic structure and elastic properties of Y-silicon nanowire junctions of fork- and bough-types were theoretically studied and effective Young modulus were calculated using the Tersoff interatomic potential. In the final stages of bending, new bonds between different parts of the Y-shaped wires are formed. It was found that the stiffness of the nanowires considered can be compared with the stiffness of carbon nanotube Y-junctions.
Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than th…
Networks of silicon nanowires possess intriguing electronic properties surpassing the predictions based on quantum confinement of individual nanowires. Employing large-scale atomistic pseudopotential computations, as yet unexplored branched nanostructures are investigated in the subsystem level, as well as in full assembly. The end product is a simple but versatile expression for the bandgap and band edge alignments of multiply-crossing Si nanowires for various diameters, number of crossings, and wire orientations. Further progress along this line can potentially topple the bottom-up approach …
Utilizing atomistic lattice dynamics and scattering theory, we study thermal transport in nanodevices made of 10 nm thick silicon nanowires, from 10 to 100 nm long, sandwiched between two bulk reservoirs. We find that thermal transport in devices differs significantly from that of suspended extended nanowires, due to phonon scattering at the contact interfaces. We show that thermal conductance and the phonon transport regime can be tuned from ballistic to diffusive by varying the surface roughness of the nanowires and their length. In devices containing short crystalline wires phonon tunneling…
A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and ther…
By means of first-principles density functional theory calculations, we find that hydrogen-passivated ultrathin silicon nanowires (SiNWs) along [100] direction with symmetrical multiple surface dangling bonds (SDBs) and boron doping can have a half-metallic ground state with 100% spin polarization, where the half-metallicity is shown quite robust against external electric fields. Under the circumstances with various SDBs, the H-passivated SiNWs can also be ferromagnetic or antiferromagnetic semiconductors. The present study not only offers a possible route to engineer half-metallic SiNWs witho…
Band gap modification for small-diameter (1 nm) silicon nanowires resulting from the use of different species for surface termination is investigated by density functional theory calculations. Because of quantum confinement, small-diameter wires exhibit a direct band gap that increases as the wire diameter narrows, irrespective of surface termination. This effect has been observed in previous experimental and theoretical studies for hydrogenated wires. For a fixed cross-section, the functional group used to saturate the silicon surface significantly modifies the band gap, resulting in relative…
Nanowires have unique optical properties [1-4] and are considered as important building blocks for energy harvesting applications such as solar cells. [2, 5-8] However, due to their large surface-to-volume ratios, the recombination of charge carriers through surface states reduces the carrier diffusion lengths in nanowires a few orders of magnitude,[9] often resulting in the low efficiency (a few percent or less) of nanowire-based solar cells. [7, 8, 10, 11] Reducing the recombination by surface passivation is crucial for the realization of high performance nanosized optoelectronic devices, bu…
Effective electron mobilities are obtained by transport measurements on InAs nanowire field-effect transistors at temperatures ranging from 10-200 K. The mobility increases with temperature below ~ 30 - 50 K, and then decreases with temperature above 50 K, consistent with other reports. The magnitude and temperature dependence of the observed mobility can be explained by Coulomb scattering from ionized surface states at typical densities. The behaviour above 50 K is ascribed to the thermally activated increase in the number of scatterers, although nanoscale confinement also plays a role as hig…
We perform classical molecular dynamics simulations to demonstrate the application of kinked silicon nanowires (KSiNWs) as nanoscale springs. The spring-like oscillation in gigahertz frequency range is successfully actuated using a similar procedure as the actuation of a classical mass spring oscillator. We detect the spring-like mechanical oscillation and some other low-frequency oscillations by the energy spectrum analysis, where a dimensional crossover phenomenon is observed for the transverse mode in KSiNWs with decreasing aspect ratio. Our findings shed light on the elastic properties of …
We investigate the relaxation dynamics of photogenerated carriers in silicon nanowires consisting of a crystalline core and a surrounding amorphous shell, using femtosecond time-resolved differential reflectivity and transmission spectroscopy at photon energies of 3.15 eV and 1.57 eV. The complex behavior of the differential transmission and reflectivity transients is the mixed contributions from the crystalline core and the amorphous silicon on the nanowire surface and the substrate where competing effects of state filling and photoinduced absorption govern the carrier dynamics. Faster relaxa…
Evidence is given for the effectiveness of InAs surface passivation by the growth of an epitaxial InAlAs shell. The electron mobility is measured as a function of temperature for both core-shell and unpassivated nanowires, with the core-shell nanowires showing a monotonic increase in mobility as temperature is lowered, in contrast to a turnover in mobility seen for the unpassivated nanowires. We argue that this signifies a reduction in low temperature ionized impurity scattering for the passivated nanowires, implying a reduction in surface states.
We consider the electronic transport properties of phosphorus (P) doped silicon nanowires (SiNWs). By combining ab initio density functional theory (DFT) calculations with a recursive Green's function method, we calculate the conductance distribution of up to 200 nm long SiNWs with different distributions of P dopant impurities. We find that the radial distribution of the dopants influences the conductance properties significantly: Surface doped wires have longer mean-free paths and smaller sample-to-sample fluctuations in the cross-over from ballistic to diffusive transport. These findings ca…
Vertically aligned silicon micro/nanowire arrays of different sizes have been synthesized by combining the modified metal-assisted chemical etching (MACE) and reactive ion etching (RIE) methods. This is a novel lithography-free method to fabricate silicon micro/nanowire arrays. The size of micro/nanowire arrays is controlled by controlling the etching rate and diameter of silica particles. The silicon micro/nanowire geometry can utilize for efficient collection of photo-generated charge carriers from impure silicon wafers, which have a short minority carrier diffusion length also act as a self…
Iron silicon oxide nanowire has been synthesized by putting single crystalline Si(100) wafer into ammonium iron sulfate, hydrogen peroxide, and triethylamine solution heated to from 70 to 100 degree in the air. The prepared iron silicon oxide nanowires with diameters of about 10nm (onto non etched Si(100) wafer) and about 75nm(onto etched Si(100) wafer) and their self assembles were characterized. The possible mechanism that accounted for the formation of iron silicon oxide nanowire is suggested based on experimental evidence.
By using molecular dynamics simulations, we study thermal conductivity of silicon nanowires (SiNWs) with different cross sectional geometries. It is found that thermal conductivity decreases monotonically with the increase of surface-to-volume ratio (SVR). More interestingly, a simple universal linear dependence of thermal conductivity on SVR is observed for SiNWs with modest cross sectional area (larger than 20 nm^2), regardless of the cross sectional geometry. As a result, among different shaped SiNWs with the same cross sectional area, the one with triangular cross section has the lowest th…
Piezoresistance is the change in the electrical resistance, or more specifically the resistivity, of a solid induced by an applied mechanical stress. The origin of this effect in bulk, crystalline materials like Silicon, is principally a change in the electronic structure which leads to a modification of the charge carriers effective mass. The last few years have seen a rising interest in the piezoresistive properties of semiconductor nanostructures, motivated in large part by claims of a giant piezoresistance effect in Silicon nanowires that is more than two orders of magnitude bigger than th…
Capacitance-voltage characteristics of individual germanium nanowire field effect transistors were directly measured and used to assess carrier mobility in nanowires for the first time; thereby removing uncertainties in calculated mobility due to device geometries, surface and interface states and gate dielectric constants and thicknesses. Direct experimental evidence showed that surround-gated nanowire transistors exhibit higher capacitance and better electrostatic gate control than top-gated devices, and are the most promising structure for future high performance nanoelectronics.
Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the nanowire channel and the gate dielectric plays a crucial role in the FET performance, and it can be responsible for unwanted effects such as hysteresis of the I-V characteristics due to threshold voltage shift when the gate voltage is applied. Using gate-voltage bias stress measurements we show that a large hysteresis of up to 40V in Si NW FETs with SiO2 dielectric is mainly due to the holes traps at the nanowire/SiO2 interface. An approach for reducing this hyster…
Using an approximate time-dependent density functional theory method, we calculate the absorption and luminescence spectra for hydrogen passivated silicon nanoscale structures with large aspect ratio. The effect of electron confinement in axial and radial directions is systematically investigated. Excited state relaxation leads to significant Stokes shifts for short nanorods with lengths less than 2 nm, but has little effect on the luminescence intensity. The formation of self-trapped excitons is likewise observed for short nanostructures only; longer wires exhibit fully delocalized excitons w…
The influence of local oxidation in silicon nanowires on hole transport, and hence the effect of varying the oxidation state of silicon atoms at the wire surface, is studied using density functional theory in conjunction with a Green's function scattering method. For silicon nanowires with growth direction along [110] and diameters of a few nanometers, it is found that the introduction of oxygen bridging and back bonds does not significantly degrade hole transport for voltages up to several hundred millivolts relative to the valence band edge. As a result, the mean free paths are comparable to…
We present a first-principles study of the electronic properties of silicon clathrate nanowires intercalated with various types of alkali or alkaline-earth atoms. We find that the band structure of the nanowires can be tuned by varying the impurity atom within the nanowire. The electronic character of the resulting systems can vary from metallic to semiconducting with direct band gaps. These properties make the nanowires specially suitable for electrical and optoelectronic applications.
We investigated the properties of stability and plasticity of silicon nanowires using molecular dynamics simulations. We considered nanowires with <100>, <110> and <112> growth directions with several diameters and surface facet configurations. We found that the wire perimeter, and not the wire diameter, is the meaningful dimensional parameter. As a result, the surface facets play a central role on the nanowire energy, that follows a universal scaling law. Additionally, we have computed the response of a silicon nanowire to external load. The results were compared to available experimental and…
Using first-principles methods we performed a theoretical study of carbon clusters in silicon carbide nanowires. We examined small clusters with carbon interstitials and antisites in hydrogen-passivated SiC nanowires growth along the [100] and [111] directions. The formation energies of these clusters were calculated as a function of the carbon concentration. We verified that the energetic stability of the carbon defects in SiC nanowires depends strongly on the composition of the nanowire surface: the energetically most favorable configuration in carbon-coated [100] SiC nanowire is not expecte…
Silicon has dominated the microelectronics industry for the last 50 years. With its zero nuclear spin isotope (28Si) and low spin orbit coupling, it is believed that silicon can become an excellent host material for an entirely new generation of devices that operate under the laws of quantum mechanics [1}. Semiconductor nanowires however, offer huge potential as the next building blocks of nano-devices due to their one-dimensional structure and properties [2]. We describe a fabrication process to prepare doped vapor-liquid-solid (VLS) grown silicon nanowire samples in a 2- and 4-terminal measu…
We report the growth of InAs$_{1-x}$Sb$_{x}$ nanowires ($0\leq x \leq 0.15$) grown by catalyst-free molecular beam epitaxy on silicon (111) substrates. We observed a sharp decrease of stacking fault density in the InAs$_{1-x}$Sb$_{x}$ nanowire crystal structure with increasing antimony content. This decrease leads to a significant increase in the field-effect mobility, this being more than three times greater at room temperature for InAs$_{0.85}$Sb$_{0.15}$ nanowires than InAs nanowires.
The potential of silicon nanowires (SiNWs), (diameter < 10 nm) to transform into rigid bundle-like structures with distinct phonon confinement under high pressure (<= 15 GPa), instead of amorphising as per previous reports, is demonstrated using in-situ Raman spectroscopy. The newly observed splitting of the second order transverse optical (2TO) Raman mode into 2TO(L) and 2TO(W) phonon modes at >= 5 GPa establishes a highly anisotropic and mode-dependent pressure response of these SiNWs. Properties of the novel structures are superior compared to other nano-structured silicon and bulk-Si in te…
Transport properties of holes in InP nanowires were calculated considering electron-phonon interaction via deformation potentials, the effect of temperature and strain fields. Using molecular dynamics, we simulate nanowire structures, LO-phonon energy renormalization and lifetime. The valence band ground state changes between light- and heavy-hole character, as the strain fields and the nanowire size are changed. Drastic changes in the mobility arise with the onset of resonance between the LO-phonons and the separation between valence subbands.
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the…
We perform molecular dynamics simulations to investigate the reduction of the thermal conductivity by kinks in silicon nanowires. The reduction percentage can be as high as 70% at room temperature. The temperature dependence of the reduction is also calculated. By calculating phonon polarization vectors, two mechanisms are found to be responsible for the reduced thermal conductivity: (1) the interchanging effect between the longitudinal and transverse phonon modes and (2) the pinching effect, i.e a new type of localization, for the twisting and transverse phonon modes in the kinked silicon nan…
Low dimensional materials provide the possibility of improved thermoelectric performance due to the additional length scale degree of freedom for engineering their electronic and thermal properties. As a result of suppressed phonon conduction, large improvements on the thermoelectric figure of merit, ZT, have been recently reported in nanostructures, compared to the raw materials' ZT values. In addition, low dimensionality can improve a device's power factor, offering an additional enhancement in ZT. In this work the atomistic sp3d5s*-spin-orbit-coupled tight-binding model is used to calculate…
Bandstructure effects in PMOS transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 20-band sp3d5s* spin-orbit-coupled (SO) atomistic tight-binding model coupled to a self consistent Poisson solver is used for the valence band dispersion calculation. A ballistic FET model is used to evaluate the capacitance and current-voltage characteristics. The dispersion shapes and curvatures are strong functions of device size, lattice orientation, and bias, and cannot be described within the effective mass approximation. The anis…
A simple and most promising oxide-assisted catalyst-free method is used to prepare silicon nitride nanowires that give rise to high yield in a short time. After a brief analysis of the state of the art, we reveal the crucial role played by the oxygen partial pressure: when oxygen partial pressure is slightly below the threshold of passive oxidation, a high yield inhibiting the formation of any silica layer covering the nanowires occurs and thanks to the synthesis temperature one can control nanowire dimensions.
The observation that the thermal conductivity of single-crystalline silicon nanowires with diameter on the length scale of 25 nm is lower than that of bulk material by two orders of magnitude has attracted the interest onto silicon as a potentially effective thermoelectric material. However, the potential interest has a hope of transforming in a practical interest only if poly-crystalline silicon can replace single crystalline silicon and the preparation of nanowires does not involve any advanced photolithography. In this work we show that a technique, based on the controlled etching and filli…
We have developed an efficient scalable kernel method for thermal transport in open systems, with which we have computed the thermal conductance of a junction between bulk silicon and silicon nanowires with diameter up to 10 nm. We have devised scaling laws for transmission and reflection spectra, which allow us to predict the thermal resistance of bulk-nanowire interfaces with larger cross sections than those achievable with atomistic simulations. Our results indicate the characteristic size beyond which atomistic systems can be treated accurately by mesoscopic theories.
From first-principles calculations, we predict that transition metal (TM) atom doped silicon nanowires have a half-metallic ground state. They are insulators for one spin-direction, but show metallic properties for the opposite spin direction. At high coverage of TM atoms, ferromagnetic silicon nanowires become metallic for both spin-directions with high magnetic moment and may have also significant spin-polarization at the Fermi level. The spin-dependent electronic properties can be engineered by changing the type of dopant TM atoms, as well as the diameter of the nanowire. Present results ar…
Temperature-dependent I-V and C-V spectroscopy of single InAs nanowire field-effect transistors were utilized to directly shed light on the intrinsic electron transport properties as a function of nanowire radius. From C-V characterizations, the densities of thermally-activated fixed charges and trap states on the surface of untreated (i.e., without any surface functionalization) nanowires are investigated while enabling the accurate measurement of the gate oxide capacitance; therefore, leading to the direct assessment of the field-effect mobility for electrons. The field-effect mobility is fo…
Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semi-empirical atomistic tight-binding model coupled to a self consistent Poisson solver is used for the dispersion calculation. A semi-classical, ballistic FET model is used to evaluate the current-voltage characteristics. It is found that the total gate capacitance is degraded from the oxide capacitance value by 30% for wires in all the considered transport orientations ([100], [110], [111]). Different wire d…
Core-shell nanowires made of Si and Ge can be grown experimentally with excellent control for different sizes of both core and shell. We have studied the structural properties of Si/Ge and Ge/Si core-shell nanowires aligned along the $[110]$ direction, with diameters up to 10.2~nm and varying core to shell ratios, using linear scaling Density Functional Theory (DFT). We show that Vegard's law, which is often used to predict the axial lattice constant, can lead to an error of up to 1\%, underlining the need for a detailed \emph{ab initio} atomistic treatment of the nanowire structure. We analys…
Utilizing sp3d5s* tight-binding band structure and wave functions for electrons and holes we show that acoustic phonon limited hole mobility in [110] grown silicon nanowires (SiNWs) is greater than electron mobility. The room temperature acoustically limited hole mobility for the SiNWs considered can be as high as 2500 cm2/Vs, which is nearly three times larger than the bulk acoustically limited silicon hole mobility. It is also shown that the electron and hole mobility for [110] grown SiNWs exceed that of similar diameter [100] SiNWs, with nearly two orders of magnitude difference for hole mo…
Strain engineering provides an effective way of tailoring the electronic and optoelectronic properties of semiconductor nanomaterials and nanodevices, giving rise to novel functionalities. Here, we present direct experimental evidence of strain-induced modifications of hole mobility in individual GaAs nanowires, using in situ transmission electron microscopy (TEM). The conductivity of the nanowires varied with applied uniaxial tensile stress, showing an initial decrease of ~5-20% up to a stress of 1~ 2 GPa, subsequently increasing up to the elastic limit of the nanowires. This is attributed to…
The microlens is a key enabling technology in optoelectronics, permitting light to be efficiently coupled to and from devices such as image sensors and light-emitting diodes. Their ubiquitous nature motivates the development of new fabrication techniques, since existing methods face challenges as microlenses are scaled to smaller dimensions. Here, we demonstrate the formation of microlenses at the tips of vertically-oriented silicon nanowires via a rapid atomic layer deposition (ALD) process. The nature of the process is such that the microlenses are centered on the nanowires, and there is a s…
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gated junctionless nanowire \emph{p}-type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with…
Low dimensional systems, nanowires, in particular, have exhibited excellent optical and electronic properties. Understanding the thermal properties in semiconductor nanowires is very important for their applications in their electronic devices. In the present study, the thermal conductivity of a freestanding silicon nanowire (NW) is estimated employing the Raman spectroscopy. The advantage of this technique is that the light source (laser) can be used both as heating and excitation source. The variations of the first-order Raman peak position of the freestanding silicon NW with respect to temp…
The mobility of charge carriers in a semiconductor nanowire is explored as a function of increasing radius, assuming low temperatures where impurity scattering dominates. The competition between increased cross-section and the concurrent increase in available scattering channels causes strongly non-monotonic dependence of the mobility on the radius. The inter-band scattering causes sharp declines in the mobility at the wire radii at which each new channel becomes available. At intermediate radii with the number of channels unchanged the mobility is seen to maintain an exponential growth even w…
We report on the growth of axial InAs-on-GaAs nanowire heterostructures on silicon by molecular beam epitaxy using 20 nm diameter Au catalysts. First, the growth parameters of the GaAs nanowire segment were optimized to achieve a pure wurtzite crystal structure. Then, we developed a two-step growth procedure to enhance the yield of vertical InAs-on-GaAs nanowires. We achieved 90% of straight InAs-on-GaAs nanowires by further optimizing the growth parameters. We investigated the composition change at the interface by energy dispersive X-ray spectroscopy and the nanowire crystal structure by tra…
Metallic contamination was key to the discovery of semiconductor nanowires, but today it stands in the way of their adoption by the semiconductor industry. This is because many of the metallic catalysts required for nanowire growth are not compatible with standard CMOS (complementary metal oxide semiconductor) fabrication processes. Nanowire synthesis with those metals which are CMOS compatible, such as aluminium and copper, necessitate temperatures higher than 450 C, which is the maximum temperature allowed in CMOS processing. Here, we demonstrate that the synthesis temperature of silicon nan…
Using empirical scheme, atomic structure of a new exotic class of silicon nanoclusters was elaborated upon the central icosahedral core (Si-IC) and pentagonal petals (Si-PP) growing from Si-IC vertexes. It was shown that Si-IC/Si-PP interface formation is energetically preferable. Some experimental observations of silicon nanostructures can be explained by presence of the proposed objects. The Extended Huckel Theory electronic structure calculations demonstrate an ability of the proposed objects to act as nanoscale tunnel junctions.
