Capacitance-voltage characteristics of individual germanium nanowire field effect transistors were directly measured and used to assess carrier mobility in nanowires for the first time; thereby removing uncertainties in calculated mobility due to device geometries, surface and interface states and gate dielectric constants and thicknesses. Direct experimental evidence showed that surround-gated nanowire transistors exhibit higher capacitance and better electrostatic gate control than top-gated devices, and are the most promising structure for future high performance nanoelectronics.
This paper presents a self-consistent numerical model for calculating the charge profile and gate capacitance and therefore obtaining C-V characterization for a gate-all-around graded nanowire MOSFET with a high mobility axially graded In0.75Ga0.25As + In0.53Ga0.47As channel incorporating strain and atomic layer deposited Al2O3/20nm Ti gate. C-V characteristics with introduction and variation of In-composition grading and also grading in doping concentration are explored.Finite element method has been used to solve Poisson's equation and Schrödinger's equation self-consistently considering wav…
The authors have investigated magnetic domain wall induced capacitance variation as a tool for the detection of magnetic reversal in magnetic nanowires for in-plane (NiFe) and out-of-plane (Co/Pd) magnetization configurations. The switching fields in the capacitance measurements match with that of the magnetoresistance measurements in the opposite sense. The origin of the magnetocapacitance has been attributed to magnetoresistance. This magnetocapacitance detection technique can be useful for magnetic domain wall studies.
Molecular dynamics computer simulations which employ the embedded-atom potential show that nanowires of gold exist as multishelled structures. We simulate double-walled gold nanowires and calculate the capacitance of a finite nanometer-size cylindrical capacitor. For the sizes for which multishelled nanowires appear in simulations we find the capacitances below one attofarad.
The bending of a nonconducting piezoelectric ZnO nanowire is simulated by finite element method calculations. The top part is bent by a lateral force, which could be applied by an atomic force microscope (AFM) tip. The generated electrical potential is 0.3 V. This relatively high signal is, however, difficult to measure, due to the low capacitance of the ZnO nanowire (4x10^{-5} pF) as compared to the capacitance of most preamplifiers (5 pF). A further problem arises from the semiconducting properties of experimentally fabricated ZnO nanowires which causes the disappearance of the voltage signa…
NiCo2O4 of varying nanostrucutures ranging from nanowires, nanoplates to nano-plates@nanowires were successfully grown on microporous (MP) Ni foams via one-step hydrothermal process. The investigation of electrochemical capacitance favors Ni-Co2O4 of nanoplates@nanowires microstructures which possesses specific capacitance of 1380.3 F/g and 1033F/g at 5A/g and 50A/g respectively and 86.7% capacitance re-tention after 5000 cycles at 30A/g. The relationship between morphology and specific capacitance was further explored by the model of surface roughness factor (RF), which is indicative of the a…
In this work, the consequence of the high band-edge density of states on the carrier statistics and quantum capacitance in transition metal dichalcogenide two-dimensional semiconductor devices is explored. The study questions the validity of commonly used expressions for extracting carrier densities and field-effect mobilities from the transfer characteristics of transistors with such channel materials. By comparison to experimental data, a new method for the accurate extraction of carrier densities and mobilities is outlined. The work thus highlights a fundamental difference between these mat…
We report the growth of InAs$_{1-x}$Sb$_{x}$ nanowires ($0\leq x \leq 0.15$) grown by catalyst-free molecular beam epitaxy on silicon (111) substrates. We observed a sharp decrease of stacking fault density in the InAs$_{1-x}$Sb$_{x}$ nanowire crystal structure with increasing antimony content. This decrease leads to a significant increase in the field-effect mobility, this being more than three times greater at room temperature for InAs$_{0.85}$Sb$_{0.15}$ nanowires than InAs nanowires.
Transport properties of holes in InP nanowires were calculated considering electron-phonon interaction via deformation potentials, the effect of temperature and strain fields. Using molecular dynamics, we simulate nanowire structures, LO-phonon energy renormalization and lifetime. The valence band ground state changes between light- and heavy-hole character, as the strain fields and the nanowire size are changed. Drastic changes in the mobility arise with the onset of resonance between the LO-phonons and the separation between valence subbands.
Temperature-dependent I-V and C-V spectroscopy of single InAs nanowire field-effect transistors were utilized to directly shed light on the intrinsic electron transport properties as a function of nanowire radius. From C-V characterizations, the densities of thermally-activated fixed charges and trap states on the surface of untreated (i.e., without any surface functionalization) nanowires are investigated while enabling the accurate measurement of the gate oxide capacitance; therefore, leading to the direct assessment of the field-effect mobility for electrons. The field-effect mobility is fo…
Utilizing sp3d5s* tight-binding band structure and wave functions for electrons and holes we show that acoustic phonon limited hole mobility in [110] grown silicon nanowires (SiNWs) is greater than electron mobility. The room temperature acoustically limited hole mobility for the SiNWs considered can be as high as 2500 cm2/Vs, which is nearly three times larger than the bulk acoustically limited silicon hole mobility. It is also shown that the electron and hole mobility for [110] grown SiNWs exceed that of similar diameter [100] SiNWs, with nearly two orders of magnitude difference for hole mo…
Strain engineering provides an effective way of tailoring the electronic and optoelectronic properties of semiconductor nanomaterials and nanodevices, giving rise to novel functionalities. Here, we present direct experimental evidence of strain-induced modifications of hole mobility in individual GaAs nanowires, using in situ transmission electron microscopy (TEM). The conductivity of the nanowires varied with applied uniaxial tensile stress, showing an initial decrease of ~5-20% up to a stress of 1~ 2 GPa, subsequently increasing up to the elastic limit of the nanowires. This is attributed to…
The mobility of charge carriers in a semiconductor nanowire is explored as a function of increasing radius, assuming low temperatures where impurity scattering dominates. The competition between increased cross-section and the concurrent increase in available scattering channels causes strongly non-monotonic dependence of the mobility on the radius. The inter-band scattering causes sharp declines in the mobility at the wire radii at which each new channel becomes available. At intermediate radii with the number of channels unchanged the mobility is seen to maintain an exponential growth even w…
Domain Morphology, Electrocaloric Response, and Negative Capacitance States of Ferroelectric Nanowires Array
Institute of Physics, National Academy of Sciences of Ukraine（乌克兰国家科学院物理研究所）；Taras Shevchenko National University of Kyiv（基辅塔拉斯舍甫琴科国立大学）；V. Lashkariov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine（乌克兰国家科学院V.拉什卡廖夫半导体物理研究所）；Slovenia Jožef Stefan Institute（斯洛文尼亚约瑟夫斯蒂芬研究所）；Frantsevich Institute for Problems in Materials Science, National Academy of Sciences of Ukraine（乌克兰国家科学院弗兰采维奇材料科学问题研究所）；Zone 5 Technologies（Zone 5科技有限公司）
The field-effect mobility of graphene devices is discussed. We argue that the graphene ballistic mean free path can only be extracted by taking into account both, the electrical characteristics and the channel length dependent mobility. In doing so we find a ballistic mean free path of 300nm at room-temperature for a carrier concentration of ~1e12/cm2 and that a substantial series resistance of around 300ohmum has to be taken into account. Furthermore, we demonstrate first quantum capacitance measurements on single-layer graphene devices.
We study the low-temperature electron mobility of InSb nanowires. We extract the mobility at 4.2 Kelvin by means of field effect transport measurements using a model consisting of a nanowire-transistor with contact resistances. This model enables an accurate extraction of device parameters, thereby allowing for a systematic study of the nanowire mobility. We identify factors affecting the mobility, and after optimization obtain a field effect mobility of $\sim2.5\mathbin{\times}10^4$ cm$^2$/Vs. We further demonstrate the reproducibility of these mobility values which are among the highest repo…
The sp3d5s*-spin-orbit-coupled atomistic tight-binding (TB) model is used for the electronic structure calculation of Si nanowires (NWs), self consistently coupled to a 2D Poisson equation, solved in the cross section of the NW. Upon convergence, the linearized Boltzmann transport theory is employed for the mobility calculation, including carrier scattering by phonons and surface roughness. As the channel is driven into inversion, for [111] and [110] NW devices of diameters D>10nm the curvature of the bandstructure increases and the hole effective mass becomes lighter, resulting in a approx. 5…
Extensive numerical calculations show that the capacitance of back-gated nanowires with various degrees of dielectric embeddings is accurately described with an effective dielectric constant as long as the difference between the dielectric thickness and the gate-nanowire distance is held constant. This is valid for dielectrics with permittivities ranging from simple air to water. However, due to screening the scaling is not valid if the dielectric lies down well below the nanowire. Moreover, when only the dielectric thickness varies the capacitance characteristics are S-shaped with three disti…
Selective area growth (SAG) of nanowires and networks promise a route toward scalable electronics, photonics and quantum devices based on III-V semiconductor materials. The potential of high-mobility SAG nanowires however is not yet fully realized, since interfacial roughness, misfit dislocations at the nanowire/substrate interface and non-uniform composition due to material intermixing all scatter electrons. Here, we explore SAG of highly lattice-mismatched InAs nanowires on insulating GaAs(001) substrates and address these key challenges. Atomically smooth nanowire/substrate interfaces are a…
The dielectric environment of thin semiconductor nanowires can affect the charge transport properties inside the wire. In this work, it is shown that Coulomb impurity scattering inside thin nanowires can be damped strongly by coating the wire with a high-k dielectric. This will lead to an increase in the mobility of free charges inside the wire.
A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and ther…
Bandstructure effects in PMOS transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 20-band sp3d5s* spin-orbit-coupled (SO) atomistic tight-binding model coupled to a self consistent Poisson solver is used for the valence band dispersion calculation. A ballistic FET model is used to evaluate the capacitance and current-voltage characteristics. The dispersion shapes and curvatures are strong functions of device size, lattice orientation, and bias, and cannot be described within the effective mass approximation. The anis…
Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than th…
A simulation framework that couples atomistic electronic structures to Boltzmann transport formalism is developed and applied to calculate the transport characteristics of thin silicon nanowires (NWs) up to 12nm in diameter. The sp3d5s*-spin-orbit-coupled atomistic tight-binding (TB) model is used for the electronic structure calculation. Linearized Boltzmann transport theory is applied, including carrier scattering by phonons, surface roughness (SRS), and impurities. We present a comprehensive investigation of the low-field mobility in silicon NWs considering: i) n- and p-type NWs, ii) [100],…
The resistivity and the mobility of Carbon doped GaAs nanowires have been studied for different doping concentrations. Surface effects have been evaluated by comparing upassivated with passivated nanowires. We directly see the influence of the surface: the pinning of the Fermi level and the consequent existence of a depletion region lead to an increase of the mobility up to 30 cm^2/(V*s) for doping concentrations lower than 3*10^18 cm^-3. Electron beam induced current measurements show that the minority carrier diffusion path can be as high as 190 nm for passivated nanowires.
The low-field electron mobility in rectangular silicon nanowire (SiNW) transistors was computed using a self-consistent Poisson-Schrödinger-Monte Carlo solver. The behavior of the phonon-limited and surface-roughness-limited components of the mobility was investigated by decreasing the wire width from 30 nm to 8 nm, the width range capturing a crossover between two-dimensional (2D) and one-dimensional (1D) electron transport. The phonon-limited mobility, which characterizes transport at low and moderate transverse fields, is found to decrease with decreasing wire width due to an increase in th…
One of the main limiting factors in the carrier mobility in semiconductor nanowires is the presence of deep trap levels. While deep-level transient spectroscopy (DLTS) has proved to be a powerful tool in analysing traps in bulk semiconductors, this technique is ineffective for the characterisation of nanowires due to their very small capacitance. Here we introduce a new technique for measuring the spectrum of deep traps in nanowires. In current-mode DLTS (I-DLTS) the temperature-dependence of the transient current through a nanowire field-effect transistor in response to an applied gate voltag…
InAs nanowires have been actively explored as the channel material for high performance transistors owing to their high electron mobility and ease of ohmic metal contact formation. The catalytic growth of non-epitaxial InAs nanowires, however, has often relied on the use of Au colloids which is non-CMOS compatible. Here, we demonstrate the successful synthesis of high yield of crystalline InAs nanowires with high yield and tunable diameters by using Ni nanoparticles as the catalyst material on amorphous SiO2 substrates. The nanowires show superb electrical properties with field-effect electron…
Effective electron mobilities are obtained by transport measurements on InAs nanowire field-effect transistors at temperatures ranging from 10-200 K. The mobility increases with temperature below ~ 30 - 50 K, and then decreases with temperature above 50 K, consistent with other reports. The magnitude and temperature dependence of the observed mobility can be explained by Coulomb scattering from ionized surface states at typical densities. The behaviour above 50 K is ascribed to the thermally activated increase in the number of scatterers, although nanoscale confinement also plays a role as hig…
We present a capacitance-voltage study for arrays of vertical InAs nanowires. MOS capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr/Au metallization as one of the capacitor's electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.
Evidence is given for the effectiveness of InAs surface passivation by the growth of an epitaxial InAlAs shell. The electron mobility is measured as a function of temperature for both core-shell and unpassivated nanowires, with the core-shell nanowires showing a monotonic increase in mobility as temperature is lowered, in contrast to a turnover in mobility seen for the unpassivated nanowires. We argue that this signifies a reduction in low temperature ionized impurity scattering for the passivated nanowires, implying a reduction in surface states.
We present an analytical calculation of the velocity of a single 180 degree domain wall in a magnetic structure with reduced thickness and/or lateral dimension under the combined action of an external applied magnetic field and an electrical current. As for the case of field-induced domain wall propagation in thick films, two motion regimes with different mobilities are obtained, below and far above the so-called Walker field. Additionally, for the case of current induced motion, a Walker-like current density threshold can be defined. When the dimensions of the system become comparable to the …
Tin iodide phosphide (SnIP), an inorganic double-helix material, is a quasi-1D van der Waals semiconductor that shows promise in photocatalysis and flexible electronics. However, our understanding of the fundamental photophysics and charge transport dynamics of this new material is limited. Here, we use time-resolved terahertz (THz) spectroscopy to probe the transient photoconductivity of SnIP nanowire films and, with insight into the highly anisotropic electronic structure from quantum chemical calculations, measure an electron mobility as high as 280 $cm^2V^{-1}s^{-1}$. Additionally, the THz…
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gated junctionless nanowire \emph{p}-type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with…
The Influence of Chemical Strains on the Electrocaloric Response, Polarization Morphology, Tetragonality and Negative Capacitance Effect of Ferroelectric Core-Shell Nanorods and Nanowires
We investigate the effects of electron and acoustic-phonon confinement on the low-field electron mobility of thin square silicon nanowires (SiNWs) that are surrounded by SiO$_2$ and gated. We employ a self-consistent Poisson-Schrödinger-Monte Carlo solver that accounts for scattering due to acoustic phonons (confined and bulk), intervalley phonons, and the Si/SiO$_2$ surface roughness. The wires considered have cross sections between 3 $\times$ 3 nm$^2$ and 8 $\times$ 8 nm$^2$. For larger wires, as expected, the dependence of the mobility on the transverse field from the gate is pronounced. At…
High quality heteroepitaxial two-dimensional (2D) InSb layers are very difficult to realize owing to the large lattice mismatch with other widespread semiconductor substrates. A way around this problem is to grow free-standing 2D InSb nanostructures on nanowire (NW) stems, thanks to the capability of NWs to efficiently relax elastic strain along the sidewalls when lattice-mismatched semiconductor systems are integrated. In this work, we optimize the morphology of free-standing 2D InSb nanoflags (NFs). In particular, robust NW stems, optimized growth parameters, and the use of reflection high-e…
Coherent quantum phase slips are expected to lead to a blockade of dc conduction in sufficiently narrow superconducting nanowires below a certain critical voltage. We present measurements of NbN nanowires in which not only is a critical voltage observed, but also in which this critical voltage may be tuned using a side-gate electrode. The critical voltage varies periodically as the applied gate voltage is varied. While the observations are qualitatively as expected for quantum interference between coherent quantum phase slip elements, the period of the tuning is orders of magnitude larger than…
We present a simple fabrication technique for lateral nanowire wrap-gate devices with high capacitive coupling and field-effect mobility. Our process uses e-beam lithography with a single resist-spinning step, and does not require chemical etching. We measure, in the temperature range 1.5-250 K, a subthreshold slope of 5-54 mV/decade and mobility of 2800-2500 $cm^2/Vs$ -- significantly larger than previously reported lateral wrap-gate devices. At depletion, the barrier height due to the gated region is proportional to applied wrap-gate voltage.
We investigate the effect of electrostatic gating on the thermoelectric power factor of p-type Si nanowires (NWs) of up to 20nm in diameter in the [100], [110] and [111] crystallographic transport orientations. We use atomistic tight-binding simulations for the calculation of the NW electronic structure, coupled to linearized Boltzmann transport equation for the calculation of the thermoelectric coefficients. We show that gated NW structures can provide ~5x larger thermoelectric power factor compared to doped channels, attributed to their high hole phonon-limited mobility, as well as gating in…
From electrodeless time-resolved microwave conductivity measurements, the efficiency of charge carrier generation, their mobility, and decay kinetics on photo-excitation were studied in arrays of Si nanowires grown by the vapor-liquid-solid mechanism. A large enhancement in the magnitude of the photoconductance and charge carrier lifetime are found depending on the incorporation of impurities during the growth. They are explained by the internal electric field that builds up, due to a higher doped sidewalls, as revealed by detailed analysis of the nanowire morphology and chemical composition.
Using molecular dynamics simulations, we study the impact of physisorbing adsorbates on the structural and mechanical evolution of gold nanowires (AuNWs) undergoing elongation. We used various adsorbate models in our simulations, with each model giving rise to a different surface coverage and mobility of the adsorbed phase. We find that the local structure and mobility of the adsorbed phase remains relatively uniform across all segments of an elongating AuNW, except for the thinning region of the wire where the high mobility of Au atoms disrupts the monolayer structure, giving rise to higher s…
The integration of advanced optoelectronic properties in nanoscale devices of group III nitride can be realized by understanding the coupling of charge carriers with optical excitations in these nanostructures. The native defect induced electron-phonon coupling in GaN nanowires are reported using various spectroscopic studies. The GaN nanowires having different native defects are grown in atmospheric pressure chemical vapor deposition technique. X-ray photoelectron spectroscopic analysis revealed the variation of Ga/N ratios in nanowires having possible native defects, with respect to their gr…
We discuss the residual carrier density (n*) near the Dirac point (DP) in graphene estimated by quantum capacitance (CQ) and conductivity measurements. The CQ at the DP has a finite value and is independent of the temperature. A similar behavior is also observed for the conductivity at the DP, because their origin is residual carriers induced externally by charged impurities. The n* extracted from CQ, however, is often smaller than that from the conductivity, suggesting that the mobility in the puddle region is lower than that in the linear region. The CQ measurement should be employed for est…
We propose a technique for achieving large improvements in carrier mobilities in 2- and 1-dimensional semiconductor nanostructures by modifying their dielectric environments. We show that by coating the nanostructures with high-$κ$ dielectrics, scattering from Coulombic impurities can be strongly damped. Though screening is also weakened, the damping of Coulombic scattering is much larger, and the resulting improvement in mobilities of carriers can be as much as an order of magnitude for thin 2D semiconductor membranes, and more for semiconductor nanowires.
InGaAs gate-all-around nanowire MOSFETs with channel length down to 50nm have been experimentally demonstrated by top-down approach. The nanowire size-dependent transport properties have been systematically investigated. It is found that reducing nanowire dimension leads to higher on-current, transconductance and effective mobility due to stronger quantum confinement and the volume inversion effect. TCAD quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume inversion effect appears at a larger dimension for InGaAs nanowire MO…
Ferroelectrics are essential in low-dimensional memory devices for multi-bit storage and high-density integration. A polar structure is a necessary premise for ferroelectricity, mainly existing in compounds. However, it is usually rare in elemental materials, causing a lack of spontaneous electric polarization. Here, we report an unexpected room-temperature ferroelectricity in few-chain Te nanowires. Out-of-plane ferroelectric loops and domain reversal are observed by piezoresponse force microscopy. Through density functional theory, we attribute the ferroelectricity to the ion-displacement cr…
We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions are realized by low energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the nanowire resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and ON/O…
N-type doping of GaAs nanowires has proven to be difficult because the amphoteric character of silicon impurities is enhanced by the nanowire growth mechanism and growth conditions. The controllable growth of n-type GaAs nanowires with carrier density as high as 1020 electron/cm3 by self-assisted molecular beam epitaxy using Te donors is demonstrated here. Carrier density and electron mobility of highly doped nanowires are extracted through a combination of transport measurement and Kelvin probe force microscopy analysis in single-wire field-effect devices. Low-temperature photoluminescence is…
Novel electronic systems forming at oxide interfaces comprise a class of new materials with a wide array of potential applications. A high mobility electron system forms at the LaAlO$_3$/SrTiO$_3$ interface and, strikingly, both superconducts and displays indications of hysteretic magnetoresistance. An essential step for device applications is establishing the ability to vary the electronic conductivity of the electron system by means of a gate. We have fabricated metallic top gates above a conductive interface to vary the electron density at the interface. By monitoring capacitance and electr…
We probe the magnetotransport properties of individual InAs nanowires in a field effect transistor geometry. In the low magnetic field regime we observe magnetoresistance that is well described by the weak localization (WL) description in diffusive conductors. The weak localization correction is modified to weak anti-localization (WAL) as the gate voltage is increased. We show that the gate voltage can be used to tune the phase coherence length ($l_ϕ$) and spin-orbit length ($l_{so}$) by a factor of $\sim$ 2. In the high field and low temperature regime we observe the mobility of devices can b…
The tunable properties of molecular materials place them among the favorites for a variety of future generation devices. In addition, to maintain the current trend of miniaturization of those devices, a departure from the present top-down production methods may soon be required and self-assembly appears among the most promising alternatives. On-surface synthesis unites the promises of molecular materials and of self-assembly, with the sturdiness of covalently bonded structures: an ideal scenario for future applications. Following this idea, we report the synthesis of functional extended nanowi…
Indium antimonide (InSb) nanowires are used as building blocks for quantum devices because of their unique properties, i.e., strong spin-orbit interaction and large Landé g-factor. Integrating InSb nanowires with other materials could potentially unfold novel devices with distinctive functionality. A prominent example is the combination of InSb nanowires with superconductors for the emerging topological particles research. Here, we combine the II-VI cadmium telluride (CdTe) with the III-V InSb in the form of core-shell (InSb-CdTe) nanowires and explore potential applications based on the elect…
Optoelectronic micro- and nanostructures have a vast parameter space to explore for modification and optimisation of their functional performance. This paper reports on a data-led approach using high-throughput single nanostructure spectroscopy to probe > 8,000 structures, allowing for holistic analysis of multiple material and optoelectronic parameters with statistical confidence. The methodology is applied to surface-guided CsPbBr$_3$ nanowires, which have complex and interrelated geometric, structural and electronic properties. Photoluminescence-based measurements, studying both the surface…
We fabricate electric double-layer field-effect transistor (EDL-FET) devices on mechanically exfoliated few-layer graphene. We exploit the large capacitance of a polymeric electrolyte to study the transport properties of three, four and five-layer samples under a large induced surface charge density both above and below the glass transition temperature of the polymer. We find that the carrier mobility shows a strong asymmetry between the hole and electron doping regime. We then employ ab-initio density functional theory (DFT) calculations to determine the average scattering lifetime from the e…
