Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardware elements, we propose a modular sparse 2d spin-qubit architecture with unit cells consisting of diagonally-oriented squares with nanowires along the edges and junctions on the corners. We show that this architecture allows for compilation strategies which outperform the best-in-class compilation strategy for 1d chains, not only asymptotically, but also down to the minimal structure of a single square. The proposed architecture exhibits favorable scaling properties which allow for balancing the trade-off between compilation overhead and co-location of classical control electronics within each square by adjusting the length of the nanowires. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes. Finally, we note that our compilation strategies, while being inspired by spin-qubits, are equally valid for any other quantum processor with sparse 2d connectivity.
Co-Designing Spectral Transformation Oracles with Hybrid Oscillator-Qubit Quantum Processors: From Algorithms to Compilation
Yale University（耶鲁大学）；University of California Santa Barbara（加州大学圣塔芭芭拉分校）；Oak Ridge National Laboratory（橡树岭国家实验室）；IBM Quantum（IBM量子）；Brookhaven National Laboratory（布鲁克海文国家实验室）；Yale Quantum Institute, Yale University（耶鲁大学量子研究所）；North Carolina State University（北卡罗来纳州立大学）
QSteed: A Resource-Virtualized and Hardware-Aware Quantum Compilation Framework for Real Quantum Computing Processors
Beijing Academy of Quantum Information Sciences（北京量子信息科学研究院）；State Key Laboratory of Low Dimensional Quantum Physics, Department of Physics, Tsinghua University（清华大学物理系低维量子物理国家重点实验室）；Beijing Key Laboratory of Fault-Tolerant Quantum Computing（北京容错量子计算北京市重点实验室）；Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所）；School of Medical Technology, Beijing Institute of Technology（北京理工大学医学技术学院）
All-to-all connectivity of Rydberg-atom-based quantum processors with messenger qubits
Russian Quantum Center（俄罗斯量子中心）；Moscow Institute of Physics and Technology（莫斯科物理技术学院）；Quantum Technology Centre and Faculty of Physics, M. V. Lomonosov Moscow State University（莫斯科国立大学量子技术中心与物理学院）；National University of Science and Technology “MISIS”（国立科技大学米西斯）；Skolkovo Institute of Science and Technology（斯科尔科沃科学技术学院）；Department of Mathematical Methods for Quantum Technologies, Steklov Mathematical Institute of Russian Academy of Sciences（俄罗斯科学院斯捷克洛夫数学研究所量子技术数学方法系）
Möbius-Guided Diagonal-Gate Compilation with Native Multiqubit Controlled-Phase Gates on Neutral-Atom Processors
Beijing Academy of Quantum Information Sciences（北京量子信息科学研究院）；Department of Computer Science and Engineering, The Chinese University of Hong Kong（香港中文大学计算机科学与工程系）；State Key Laboratory of Low Dimensional Quantum Physics, Department of Physics, Tsinghua University（清华大学物理系低维量子物理国家重点实验室）；Frontier Science Center for Quantum Information（量子信息前沿科学中心）
Lifting connectivity bottlenecks in superconducting quantum processors via enriched native two-qubit gates
China Telecom Quantum Information Technology Group Co., Ltd.（中国电信量子信息技术集团有限公司）；Quantum Research Institute of China Telecom（中国电信量子研究院）；Department of Computer Science and Technology, Tsinghua University（清华大学计算机科学与技术系）；TraverseQuantum Co., Ltd.（Tianyu Quantum Co., Ltd.）；Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology（香港科技大学电子与计算机工程系）
A Platform-aware Compilation Framework for Fault-tolerant Quantum Computation
NNF Quantum Computing Programme, Niels Bohr Institute, University of Copenhagen（哥本哈根大学尼尔斯·玻尔研究所）；Quantum Engineering Centre for Doctoral Training, H. H. Wills Physics Laboratory and School of Electrical, Electronic, and Mechanical Engineering, University of Bristol（布里斯托大学电气、电子和机械工程学院）；Nano-Science Center and Department of Chemistry, University of Copenhagen（哥本哈根大学纳米科学中心及化学系）
Late Breaking Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits
eBRAIN Lab, Division of Engineering, New York University (NYU) Abu Dhabi（纽约大学阿布扎比分校工程学院）；Center for Quantum and Topological Systems, NYUAD Research Institute, NYU Abu Dhabi（纽约大学阿布扎比分校研究学院量子与拓扑系统中心）
Experimental Quantum End-to-End Learning on a Superconducting Processor
机器学习可以由量子计算机提供大量动力，因为它具有巨大的希尔伯特空间和固有的量子并行性。为了追求具有噪声的中等规模量子设备的机器学习的量子优势，提出了可以以端到端的方式设计学习模型，即，通过直接可操纵的控制脉冲来参数化量子测量，而无需电路设计和编译。这种无门模型是硬件友好的，可以充分利用有限的量子资源。在这里，我们报告了在超导处理器上实现量子端到端机器学习的第一个实验。在MNIST（Mixed National Institute of Standards and Technology）数据库中，经过训练的模型可以对两个手写数字（通过两个量子位）实现98%的识别准确率，对四个数字（通过三个量子位）实现89%的识别准确率。实验结果展示了量子端到端学习的巨大潜力，当有更多的量子比特可用时，它可以解决复杂的现实世界任务。
