可重构基于总线的量子路由器用于模块化超导处理器
Reconfigurable Bus-based Quantum Router for Modular Superconducting Processors
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中文总结 AI 辅助
本文提出一种基于总线的可重构量子路由器，通过磁通可调SQUID耦合器实现并行CZ门，减少SWAP和CZ计数，提升模块化超导处理器性能。
中文摘要 AI 辅助
扩展超导量子处理器需要提供非局域连接和并行纠缠操作的互连。最近邻耦合要求远距离相互作用通过SWAP网络进行路由，这增加了原生双量子门计数，并可能延长电路关键路径。在此，我们介绍一种用于模块化超导处理器的基于总线的可重构量子路由器。磁通可调SQUID耦合器选择性地将接口量子比特连接到两个共享总线，允许相消干涉抑制空闲相互作用，同时支持两个不相交的受控-Z（CZ）门并行执行。全系统哈密顿量模拟得出并行门误差在$10^{-3}$量级，开放系统分析确定了高保真操作所需的相干性要求。我们进一步使用硬件感知编译和资源受限调度评估电路级后果。对于36量子比特的量子傅里叶变换（QFT）、QAOA-MaxCut和随机配对电路，相对于匹配的二维网格，路由器将中位SWAP计数减少最多$34\%$，原生CZ计数减少最多$20\%$。端到端深度减少依赖于电路，对于QAOA-MaxCut达到$20\%$，而对于QFT尽管其门计数较低，减少效果可忽略。这些结果表明，增强的连接性和可调度的并行性提供了不同的优势，将路由器确立为模块化超导量子处理器的编译器可见硬件资源。
英文摘要
Scaling superconducting quantum processors requires interconnects that provide both non-local connectivity and parallel entangling operations. While current quantum routers offer greater connectivity than nearest-neighbour topologies, their support for parallel, independently addressable two-qubit gates remains fundamentally limited, imposing severe compilation overheads that constitute a critical bottleneck. Here we introduce a bus-based reconfigurable quantum router that enables parallel controlled-$Z$ (CZ) gates for modular superconducting processors. Constructed from a flux-tunable SQUID network, the router selectively connects interface qubits to two shared buses, allowing destructive interference to suppress idle interactions while supporting two disjoint CZ gates in parallel. Full-system Hamiltonian simulations yield parallel-gate infidelities ranging from $7.9\times10^{-4}$ to $1.8\times10^{-3}$ under the operating conditions considered, and an open-system analysis identifies the coherence requirements for high-fidelity operation. We further assess the circuit-level consequences using hardware-aware compilation and resource-constrained scheduling. For the 36-qubit quantum Fourier transform (QFT), QAOA-MaxCut, and random-pairing circuits, the router reduces the median SWAP count by up to $34\%$ and the native CZ count by up to $20\%$ relative to a matched two-dimensional grid. Circuit-depth reductions are workload-dependent, reaching $20\%$ for QAOA-MaxCut but remaining negligible for the QFT despite its lower gate count. These results show that enhanced connectivity and schedulable parallelism provide complementary benefits for connectivity-intensive algorithms, establishing the router as a compiler-visible hardware resource and providing a scalable architectural pathway toward constructing highly connected modular superconducting quantum processors.
发表机构
- Information Engineering University（信息工程大学）
机构由 AI 辅助整理，请以论文原文为准。
