In some physical implementations of quantum computers, 2-qubit operations can be applied only on certain pairs of qubits. Compilation of a quantum circuit into one compliant to such qubit connectivity constraint results in an increase of circuit depth. Various compilation algorithms were studied, yet what this depth overhead is remains elusive. In this paper, we fully characterize the depth overhead by the routing number of the underlying constraint graph, a graph-theoretic measure which has been studied for 3 decades. We also give reduction algorithms between different graphs, which allow compilation for one graph to be transferred to one for another. These results, when combined with existing routing algorithms, give asymptotically optimal compilation for all commonly seen connectivity graphs in quantum computing.
Quantum circuit compilation with constant overhead
Google Quantum AI（谷歌量子人工智能）；Stanford University（斯坦福大学）；MIT（麻省理工学院）；Institute for Quantum Computing, University of Waterloo and Perimeter Institute for Theoretical Physics（滑铁卢大学量子计算研究所与佩里尔理论物理研究所）
Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardw…
Qubit routing is a key problematic related to quantum circuit compilation. It consists in rewriting a quantum circuit by adding the least possible number of instructions to make the circuit compliant with some architecture's connectivity constraints. Usually, this problem is tackled via either SWAP insertion techniques or re-synthesis of portions of the circuit using architecture aware synthesis algorithms. In this work, we propose a meta-heuristic that couples the iterative approach of SWAP insertion techniques with greedy architecture aware synthesis routines. We propose two new compilation …
In leading fault-tolerant quantum computing schemes, accurate transformation are obtained by a two-stage process. In a first stage, a discrete, universal set of fault-tolerant operations is obtained by error-correcting noisy transformations and distilling resource states. In a second stage, arbitrary transformations are synthesized to desired accuracy by combining elements of this set into a circuit. Here, we present a scheme which merges these two stages into a single one, directly distilling complex transformations. We find that our scheme can reduce the total overhead to realize certain gat…
This paper addresses the problem of finding the depth overhead that will be incurred when running quantum circuits on near-term quantum computers. Specifically, it is envisaged that near-term quantum computers will have low qubit connectivity: each qubit will only be able to interact with a subset of the other qubits, a reality typically represented by a qubit interaction graph in which a vertex represents a qubit and an edge represents a possible direct 2-qubit interaction (gate). Thus the depth overhead is unavoidably incurred by introducing swap gates into the quantum circuit to enable gene…
QROB: Quantifying Realization Overhead in Quantum Compilation via Reverse Construction
Beijing Academy of Quantum Information Sciences（北京量子信息科学研究院）；Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所）；Institute of Physics, Chinese Academy of Sciences（中国科学院物理研究所）；Hefei National Laboratory（合肥国家实验室）
Logical Resource Estimation for Quantum State Preparation with Compilation
Lawrence Berkeley National Laboratory（劳伦斯伯克利国家实验室）；University of California, Los Angeles（加州大学洛杉矶分校）；Duke University（杜克大学）；University of California, Berkeley（加州大学伯克利分校）
Current proposals for quantum compilers require the synthesis and optimization of linear reversible circuits and among them CNOT circuits. Since these circuits represent a significant part of the cost of running an entire quantum circuit, we aim at reducing their size. In this paper we present a new algorithm for the synthesis of CNOT circuits based on the solution of the syndrome decoding problem. Our method addresses the case of ideal hardware with an all-to-all qubit connectivity and the case of near-term quantum devices with restricted connectivity. For both cases, we present benchmarks sh…
Vast numbers of qubits will be needed for large-scale quantum computing due to the overheads associated with error correction. We present a scheme for low-overhead fault-tolerant quantum computation based on quantum low-density parity-check (LDPC) codes, where long-range interactions enable many logical qubits to be encoded with a modest number of physical qubits. In our approach, logic gates operate via logical Pauli measurements that preserve both the protection of the LDPC codes as well as the low overheads in terms of the required number of additional qubits. Compared with surface codes wi…
A Platform-aware Compilation Framework for Fault-tolerant Quantum Computation
NNF Quantum Computing Programme, Niels Bohr Institute, University of Copenhagen（哥本哈根大学尼尔斯·玻尔研究所）；Quantum Engineering Centre for Doctoral Training, H. H. Wills Physics Laboratory and School of Electrical, Electronic, and Mechanical Engineering, University of Bristol（布里斯托大学电气、电子和机械工程学院）；Nano-Science Center and Department of Chemistry, University of Copenhagen（哥本哈根大学纳米科学中心及化学系）
In the last decades, we have witnessed the rapid growth of Quantum Computing. In the current Noisy Intermediate-Scale Quantum (NISQ) era, the capability of a quantum machine is limited by the decoherence time, gate fidelity and the number of Qubits. Current quantum computing applications are far from the real "quantum supremacy" due to the fragile physical Qubits, which can only be entangled for a few microseconds. Recent works use quantum optimal control to reduce the latency of quantum circuits, thereby effectively increasing quantum volume. However, the key challenge of this technique is th…
Late Breaking Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits
eBRAIN Lab, Division of Engineering, New York University (NYU) Abu Dhabi（纽约大学阿布扎比分校工程学院）；Center for Quantum and Topological Systems, NYUAD Research Institute, NYU Abu Dhabi（纽约大学阿布扎比分校研究学院量子与拓扑系统中心）
Optimized Compilation of Logical Clifford Circuits
Fraunhofer IIS, Fraunhofer Institute for Integrated Circuits IIS（弗劳恩霍夫集成电路研究所）；University of Würzburg（维尔茨堡大学）；Friedrich-Alexander-Universität Erlangen-Nürnberg（埃尔朗根-纽伦堡弗里德里希·阿历克西斯大学）
It is imperative to compile quantum circuits for Noisy Intermediate-Scale Quantum (NISQ) devices because of the limited connectivity of physical qubits and the high error rates of gate operations. One of the most critical steps in quantum circuit compilation is qubit routing, an NP-Hard problem that involves placing and moving logical qubits to minimize compilation overhead. In this study, we propose ISing mAchine Assisted Quantum compiler (ISAAQ) to perform qubit routing with Ising machines, which can efficiently solve Quadratic Unconstrained Binary Optimization (QUBO) problems. ISAAQ accurat…
Risk-aware neural pulse compilation of continuously parameterized single-qubit gates with optimal-control benchmarking and NMR hardware validation
Koç University（科奇大学）；TÜBİTAK Research Institute for Fundamental Sciences (TBAE)（土耳其科学技术研究委员会基础科学研究院（TBAE））；Middle East Technical University（中东理工大学）；Shenzhen SpinQ Technology Co., Ltd.（深圳本源量子技术有限公司）
Scalable Low-overhead Superconducting Non-local Coupler with Exponentially Enhanced Connectivity
Tsinghua University（清华大学）；Beijing Academy of Quantum Information Sciences（北京量子信息科学研究院）；Institute of Physics, Chinese Academy of Science（中国科学院物理研究所）；University of Chinese Academy of Sciences（中国科学院大学）；Hefei National Laboratory（合肥国家实验室）
Quantum LDPC codes may provide a path to build low-overhead fault-tolerant quantum computers. However, as general LDPC codes lack geometric constraints, naïve layouts couple many distant qubits with crossing connections which could be hard to build in hardware and could result in performance-degrading crosstalk. We propose a 2D layout for quantum LDPC codes by decomposing their Tanner graphs into a small number of planar layers. Each layer contains long-range connections which do not cross. For any CSS code with a degree-$δ$ Tanner graph, we design stabilizer measurement circuits with depth at…
Parameterized circuit instantiation is a common technique encountered in the generation of circuits for a large class of hybrid quantum-classical algorithms. Despite being supported by popular quantum compilation infrastructures such as IBM Qiskit and Google Cirq, instantiation has not been extensively considered in the context of circuit compilation and optimization pipelines. In this work, we describe algorithms to apply instantiation during two common compilation steps: circuit optimization and gate-set transpilation. When placed in a compilation workflow, our circuit optimization algorithm…
