High throughput experimental methods are known to accelerate the rate of research, development, and deployment of electronic materials. For example, thin films with lateral gradients in composition, thickness, or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect material properties under varying measurement conditions. Similarly, multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance. In this work, we apply these high throughput experimental methods to thin film transistors (TFTs), demonstrating combinatorial device fabrication and semi-automated characterization using sputtered Indium-Gallium-Zinc-Oxide (IGZO) TFTs as a case study. We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library, such as channel thickness and length, channel cation compositions, and oxygen atmosphere during deposition. We also present a semi-automated method to measure the 44 devices fabricated on a 50x50mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time. Finally, we propose a fully automated characterization system for similar TFT libraries, which can be coupled with high throughput data analysis. These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.
Metal oxide thin-film transistors are fast becoming a ubiquitous technology for application in driving backplanes of organic light-emitting diode displays. Currently all commercial products rely on metal oxides processed via physical vapor deposition methods. Transition to simpler, higher throughput manufacturing methods such as solution-based processes, are currently been explored as cost-effective alternatives. However, developing printable oxide transistors with high carrier mobility and bias-stable operation has proved challenging. Here we show that hybrid multilayer channels composed of a…
In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semicondu…
p-type doping from the dielectric/semiconductor interface of a SnO2 thin film transistor (TFT) has been utilized to develop high carrier mobility balanced ambipolar oxide-transistor. To introduce this interfacial-doping, bottom-gate top-contact TFTs have been fabricated by using two different ion-conducting oxide dielectrics which contain trivalent atoms. These ion-conducting dielectrics are LilnO2 and LiGaO2 respectively, containing mobile Li+ ion. During SnO2 thin film fabrication on top of the ionic dielectric, those trivalent atoms allow p- doping to the interfacial SnO2 layer to introduce…
In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance,…
A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current IDS modulation by a gate-source voltage VGS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the…
To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.
High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analog applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A record high transconductance of 4 S/mm is also achieved among all transistors with a planar stru…
In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ωmm and a low contact resistivity of 1.1{\times}10-7 Ωcm2. The ITO transistor with a recessed channel and …
We report on a giant persistent photoconductivity (PPC) induced semiconductor-to-conductor like transition in zinc-tin-oxide (ZTO) photo-thinfilm transistors (TFT). The active ZTO channel layer was prepared by remote-plasma reactive sputtering and possesses an amorphous structure. Under subbandgap excitation of ZTO with UV light, the photocurrent reaches as high as ~10 -4 A (a photo-to-dark current ratio of ~10 7) and remains close to this high value after switching off the light. During this time, the ZTO TFT exhibits gigantic PPC with long-lasting recovery time, which leads the ZTO compound …
In this paper, we present a new theoretical model for the dielectrophoresis (DEP) process of the single-walled carbon nanotubes (SWCNT). We obtain a different frequency interval for the alignment of wide energy gap semiconductor SWCNTs which shows a considerable difference with the prevalent model. For this, we study two specific models namely, the spherical model and the ellipsoid model to estimate the frequency interval. Then, we perform the DEP process and use the obtained frequencies (of spherical and ellipsoid models) for the alignment of the SWCNTs. Our empirical results declare the theo…
The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2/Vs in ambient conditions, which we attribute to the …
Within the subgap of amorphous oxide semiconductors like amorphous indium gallium zinc oxide (a-IGZO) are donor-like and acceptor-like states that control the operational physics of optically transparent thin-film transistors (TFTs). Hydrogen incorporation into the channel layer of a top-gate a-IGZO TFT exists as an electron donor that causes an observed negative shift in the drain current-gate voltage ($\mathrm{I_{D} - V_{G}}$) transfer curve turn-on voltage. Normally, hydrogen is thought to create shallow electronic states just below the conduction band mobility edge, with the donor ionizati…
Gate-pulse-induced recombination, known as the charge pumping (CP), is a fundamental carrier recombination process, and has been utilized as a method for analyzing electrical properties of defects (or dangling bonds) at the transistor interfaces, which is now recognized to be well-matured and conventional. Nevertheless, neither the origin (the bonding configuration) of the defects responsible for the CP, nor their detailed recombination sequence has been clarified yet for Si metal-oxide-semiconductor (MOS) interfaces. In order to address these problems, we investigated the CP under spin resona…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide thickness. Specifically, for symmetric double gate (DG) FETs the scale length (Λ) varies linearly with the gate oxide thickness(t_{ox}) as Λ ~ 3/4t_{ox}. The gate oxide dielectric permittivity and the semiconductor channel thickness do not affect the device electrostatics for such device geometries. For an asymmetric device such as single gate (SG) FETs, the…
Transparent electrodes (TEs) made of metallic nanowires, such as Ag, Au, Cu, and Ni, have attracted rising attention for several reasons: 1) they can act as a substitute for tin oxide-based TEs such as indium-tin oxide (ITO) and fluorine-doped tin oxide (FTO); 2) various methods exist for fabricating such TEs such as filtration, spraying and meyer bar coating; 3) greater compatibility with different substrates can be achieved due to the variety of fabrication methods; and 4) extra functions in addition to serving as electrodes, such as catalytic abilities, can be obtained due to the metals tha…
A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of anti-ambipolar Ga…
Two-dimensional (2D) semiconductors are promising channel materials for continued downscaling of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, their full potential continues to be limited by a lack of scalable high-k dielectrics that can achieve atomically smooth interfaces, small equivalent oxide thicknesses (EOT), excellent gate control, and low leakage currents. Here, we report liquid metal printed ultrathin and scalable Ga2O3 dielectric for 2D electronics and electro-optical devices. We directly visualize the atomically smooth Ga2O3/WS2 interfaces enabled by the c…
The advances in micro-size and in-plane supercapacitors lead to produce the miniaturizing energy storage devices in portable and bendable electronics. Micro-supercapacitors have unique electrochemical performance, such as high power density, fast charging, long cycle life, and high safety. The reduction time and cost in the fabrication processes of micro-supercapacitors are important factors in micro-fabrication technology. In this work, a simple, scalable and cost-effective fabrication of interdigitated reduced graphene oxide@polyaniline flexible micro-supercapacitors is presented. We found t…
A novel 2-dimensional electron gas (2DEG) system with high-mobility was discovered at the interface of two perovskite oxides, a polar orthorhombic perovskite LaScO3 (LSO) and a nonpolar cubic perovskite BaSnO3 (BSO). Upon depositing the LSO film on the BSO film, the conductance enhancement and the resulting 2DEG density (n2D) was measured. Comparing the results with the previously reported LaInO3/BaSnO3 (LIO/BSO) polar interface, we applied the interface polarization model to the LSO/BSO system, in which the polarization exists only over 4 pseudocubic unit cells in LSO from the interface and v…
The release process for the fabrication of freestanding oxide microstructures relies on appropriate, controllable and repeatable wet etching procedures. SrTiO3 is among the most employed substrates for oxide thin films growth and can be decomposed in HF:water solution. Such process is strongly anisotropic and is affected by local defects and substrate cut-plane. We analyze the etching behavior of SrTiO3 substrates having (100), (110), and (111) cut-planes during immersion in a 5% HF:water solution. The etching process over the three substrates is compared in terms of pitting, anisotropy, macro…
Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are of potential to use in non-volatile memory technology, but suffer from short retention times, which limits their wider application. Here we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, ro…
When transistor gate insulators have nanometer-scale equivalent oxide thickness (EOT), the gate capacitance ($C_\textrm{G}$) becomes smaller than the oxide capacitance ($C_\textrm{ox}$) due to the quantum capacitance and charge centroid capacitance of the channel. Here, we study the capacitance of monolayer MoS$_\textrm{2}$ as a prototypical two-dimensional (2D) channel while considering spatial variations in the potential, charge density, and density of states. At 0.5 nm EOT, the monolayer MoS$_\textrm{2}$ capacitance is smaller than its quantum capacitance, limiting the single-gated $C_\text…
Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with a 50 nm fin structure. For high-quality interface between \b{eta}-Ga2O3 and gate dielectric, atomic layer-deposited 15-nm-thick aluminum oxide (Al2O3) was utilized with Tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV/dec, high drain curren…
In this paper, we investigated the performance of thin-film transistors (TFTs) with different channel configurations including single-active-layer (SAL) Sn-Zn-O (TZO), dual-active-layers (DAL) In-Sn-O (ITO)/TZO, and triple-active-layers (TAL) TZO/ITO/TZO. The TAL TFTs were found to combine the advantages of SAL TFTs (a low off-state current) and DAL TFTs (a high mobility and a low threshold voltage). The proposed TAL TFTs exhibit superior electrical performance, e.g. a high on-off state current ratio of 2*10^8, a low threshold voltage of 0.52 V, a high saturation mobility of 145.2 cm2/Vs, and …
We have experimentally and theoretically investigated the electron spin transport and spin distribution at room temperature in a Si two-dimensional (2D) inversion channel of back-gate-type spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The magnetoresistance ratio of the spin MOSFET with a channel length of 0.4$μ$m was increased by a factor of 6 from that in our previous paper [Phys. Rev. B 99, 165301 (2019)] by lowering the parasitic resistances at the source/drain junctions with highly-phosphorus-doped n+-Si regions and by increasing the lateral electric field in the …
We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS$_2$ field effect transistors (FETs). The MoS$_2$ FETs are fabricated using a wafer-scale process on 8 $μ$m thick polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS$_2$ sheets, grown with different processes and showing different thicknesses, are analyzed and compared from the single device fabrication and characterization steps to the circuit level. The power detector prototypes exploit the nonlinearity of the transist…
Lead-halide perovskites emerged as novel semiconducting materials suitable for a variety of optoelectronic applications. However, fabrication of reliable perovskite field-effect transistors (FETs), the devices necessary for the fundamental and applied research on charge transport properties of this class of materials, has proven challenging. Here we demonstrate high-performance perovskite FETs based on epitaxial, single crystalline thin films of cesium lead bromide (CsPbBr3). An improved vapor-phase epitaxy has allowed growing truly large-area, atomically flat films of this perovskite with exc…
