Spin transport in Si-based spin metal-oxide-semiconductor field-effect transistors: Spin drift effect in the inversion channel and spin relaxation in the n+-Si source/drain regions
We have experimentally and theoretically investigated the electron spin transport and spin distribution at room temperature in a Si two-dimensional (2D) inversion channel of back-gate-type spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The magnetoresistance ratio of the spin MOSFET with a channel length of 0.4$μ$m was increased by a factor of 6 from that in our previous paper [Phys. Rev. B 99, 165301 (2019)] by lowering the parasitic resistances at the source/drain junctions with highly-phosphorus-doped n+-Si regions and by increasing the lateral electric field in the channel along the electron transport, called "spin drift". Clear Hanle signals with some oscillation peaks were observed for the spin MOSFET with a channel length of 10 $μ$ m under the lateral electric field, indicating that the effective spin diffusion length is dramatically enhanced by the spin drift. By taking into account the n+-Si regions and the spin drift in the channel, one-dimensional analytic functions were derived for analyzing the effect of the spin drift on the spin transport through the channel and these functions were found to explain almost all the experimental results. From the calculated spin current and spin distribution, it was revealed that almost all the spins are unflipped during the spin-drift-assisted transport through the 0.4-$μ$m-long inversion channel, but the most part of the injected spins from the source electrode are relaxed in the n+-Si regions of both the source and drain junctions. This means that the spin drift is useful and precise design of the device structure is essential to obtain a higher magnetoresistance ratio. Furthermore, we showed that the effective spin resistances that are introduced in this study are very helpful to understand how to improve the magnetoresistance ratio of spin MOSFETs for practical use.
In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semicondu…
We report on the numerical and theoretical results of sub-THz and THz detection by a current-driven InGaAs/GaAs plasmonic Field-Effect Transistor (TeraFET). New equations are developed to account for the channel length dependence of the drain voltage and saturation current. Numerical simulation results demonstrate that the effect of drain bias current on the source-to-drain response voltage (dU) varies with the device channel length. In a long-channel TeraFET where plasmonic oscillations cannot reach the drain, dU is always positive and rises rapidly with increasing drain current. For a short …
We investigate the operation of dual-gate reconfigurable field-effect transistor (RFET) in the programgate at drain (PGAD) and program-gate at source (PGAS) configurations. To this end, dual-gate silicon nanowire (SiNW) FETs are fabricated based on anisotropic wet chemical silicon etching and nickel silicidation yielding silicide-SiNW Schottky junctions at source and drain. Whereas in PGAD-configuration ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky-barrier. Operating the RFET in PGAS configuration yields a switching behavior close to a con…
Novel devices such as tunneling field-effect transistors (FETs) and ferroelectric FETs have been demonstrated to break the subthreshold swing (SS) limit with sub-60 mV/decade switching for further low voltage/low power applications. In this paper, SS of sub-60 mV/dec was firstly observed in InAlN/GaN high electron mobility transistors (HMETs): an average SS of 30 mV/dec over three orders of magnitude in drain-source (Ids) and a minimum point-by-point SS of 15 mV/dec were achieved in the InAlN/GaN HEMTs with gate length (Lg) of 40 nm. It is found that SS decreases with drain-source voltage (Vds…
Gate-pulse-induced recombination, known as the charge pumping (CP), is a fundamental carrier recombination process, and has been utilized as a method for analyzing electrical properties of defects (or dangling bonds) at the transistor interfaces, which is now recognized to be well-matured and conventional. Nevertheless, neither the origin (the bonding configuration) of the defects responsible for the CP, nor their detailed recombination sequence has been clarified yet for Si metal-oxide-semiconductor (MOS) interfaces. In order to address these problems, we investigated the CP under spin resona…
High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analog applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A record high transconductance of 4 S/mm is also achieved among all transistors with a planar stru…
In this work it is reported a vertical electrolyte transistor (VET) whose structure is based on stacked layers as described below: bottom contact (source or drain) - channel - permeable intermediate electrode (drain or source) - ion gel (electrolyte gate dielectric) - gate top contact. This VET depicts versatility to work as Electrolyte-Gated Vertical Organic Field Effect Transistor (Electrolyte-Gated VOFET) or Vertical Organic Electrochemical Transistor (VOECT) as never reported before. The distinction of these operation modes is regarding to the transistor transconductance that occurs due to…
Metal oxide thin-film transistors are fast becoming a ubiquitous technology for application in driving backplanes of organic light-emitting diode displays. Currently all commercial products rely on metal oxides processed via physical vapor deposition methods. Transition to simpler, higher throughput manufacturing methods such as solution-based processes, are currently been explored as cost-effective alternatives. However, developing printable oxide transistors with high carrier mobility and bias-stable operation has proved challenging. Here we show that hybrid multilayer channels composed of a…
The performance of ultra-wide band gap materials like $β$-Ga$_\mathrm{2}$O$_\mathrm{3}$ is critically dependent on achieving high average electric fields within the active region of the device. In this report, we show that high-k gate dielectrics like BaTiO$_\mathrm{3}$ can provide an efficient field management strategy by improving the uniformity of electric field profile in the gate-drain region of lateral field effect transistors. Using this strategy, we were able to achieve high average breakdown fields of 1.5 MV/cm and 4 MV/cm at gate-drain spacing (L$_\mathrm{gd}$) of 6 um and 0.6 um res…
The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2/Vs in ambient conditions, which we attribute to the …
In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance,…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide thickness. Specifically, for symmetric double gate (DG) FETs the scale length (Λ) varies linearly with the gate oxide thickness(t_{ox}) as Λ ~ 3/4t_{ox}. The gate oxide dielectric permittivity and the semiconductor channel thickness do not affect the device electrostatics for such device geometries. For an asymmetric device such as single gate (SG) FETs, the…
p-type doping from the dielectric/semiconductor interface of a SnO2 thin film transistor (TFT) has been utilized to develop high carrier mobility balanced ambipolar oxide-transistor. To introduce this interfacial-doping, bottom-gate top-contact TFTs have been fabricated by using two different ion-conducting oxide dielectrics which contain trivalent atoms. These ion-conducting dielectrics are LilnO2 and LiGaO2 respectively, containing mobile Li+ ion. During SnO2 thin film fabrication on top of the ionic dielectric, those trivalent atoms allow p- doping to the interfacial SnO2 layer to introduce…
In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ωmm and a low contact resistivity of 1.1{\times}10-7 Ωcm2. The ITO transistor with a recessed channel and …
A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current IDS modulation by a gate-source voltage VGS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the…
In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon FETs in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/μm (near 20 mA/μm) is achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain curr…
Two-dimensional (2D) semiconductors are promising channel materials for continued downscaling of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, their full potential continues to be limited by a lack of scalable high-k dielectrics that can achieve atomically smooth interfaces, small equivalent oxide thicknesses (EOT), excellent gate control, and low leakage currents. Here, we report liquid metal printed ultrathin and scalable Ga2O3 dielectric for 2D electronics and electro-optical devices. We directly visualize the atomically smooth Ga2O3/WS2 interfaces enabled by the c…
