AI 中文总结
该研究提出并制备了无平坦化或中隙受主阻挡层的垂直氧化镓ISEFET，其阈值电压2 V、开关比>1e7，性能可与现有垂直晶体管媲美，适用于宽禁带半导体器件的高通量原型制作与大规模制造。
AI 中文摘要
我们提出并演示了首款无需平坦化回刻工艺或中隙受主区域的垂直氧化镓器件架构。隔离源电极场效应晶体管（ISEFET）采用介质阻挡层，以接入从顶部鳍式金属延伸出的隔离源极焊盘。通过电子束光刻制备了尺寸缩小的多鳍式沟道，其宽度为200 nm，同时制备源极焊盘并刻蚀至约1.2 μm的沟槽深度。所制备器件呈现增强型模式工作，阈值电压为2 V，开关比大于1e7，具备优异的栅极调制特性。该器件性能与现有垂直晶体管相当，适用于未来氧化镓及其他宽禁带半导体器件的高通量原型制作与大规模制造。
英文摘要
We propose and demonstrate the first vertical Gallium oxide device architecture without the use of planarization etch back processes or mid-gap acceptor regions. The Isolated Source Electrode Field Effect Transistor (ISEFET) incorporates a dielectric blocking layer to access an isolated source pad extending from the top fin metal. Scaled multi-fin channels were formed by electron beam lithography with a width of 200 nm along with the source pads and then etched to a trench depth of ~1.2 um. The fabricated devices showed enhancement mode operation with threshold voltage of 2 V and on-off ratio > 1e7 with excellent gate modulation characteristics. The resulting device proved to be comparable to existing vertical transistors and suitable for high-throughput prototyping and large-scale manufacturing of future Gallium oxide and other wide bandgap semiconductor devices.
Comments11 pages, 5 figures
