Laser Processing For 3D Junctionless Transistor Fabrication
D. Bosch, P. Acosta Alba, S. Kerdiles, V. Benevent, C. Perrot, J. Lassarre, J. Richy, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Beranger, D. L… 展开作者
D. Bosch, P. Acosta Alba, S. Kerdiles, V. Benevent, C. Perrot, J. Lassarre, J. Richy, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Beranger, D. Lattard, J. P. Colinge, F. Balestra, F. Andrieu
To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.
In this work, a physics based model is developed to calculate the hole mobility of ultra-thin-body double-gate junctionless transistors. Six-band $k\cdot p$ Schrödinger equation and Poisson equation are solved self-consistently. The obtained wave-functions and energies are stored in look-up tables. Hole mobility can be derived using the Kubo-Greenwood formula accounting for impurity, acoustic and optical phonon, and surface roughness scattering. Initial benchmark results are shown.
A Comprehensive Study of Charge-Carrier Mobility in Double Lateral-Gate Silicon Junctionless Transistors
Laye Rooyan Part, Isfahan Science and Technology Town（拉耶鲁扬部分，伊斯法罕科技城）；Department of Physics, Isfahan University of Technology（伊斯法罕理工大学物理系）；Institute of Microengineering and Nanoelectronics, Universiti Kebangsaan Malaysia（马来西亚国立大学微工程与纳米电子研究所）；Department of Electrical and Computer Engineering, University of Texas at Dallas（德克萨斯大学达拉斯分校电气与计算机工程系）
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gated junctionless nanowire \emph{p}-type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with…
The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultr…
This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the first-order perturbation theory for calculating eigenstates and corresponding wave functions obtained by the Schrodinger equation in the cylindrical coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step towar…
In this paper, we present a new theoretical model for the dielectrophoresis (DEP) process of the single-walled carbon nanotubes (SWCNT). We obtain a different frequency interval for the alignment of wide energy gap semiconductor SWCNTs which shows a considerable difference with the prevalent model. For this, we study two specific models namely, the spherical model and the ellipsoid model to estimate the frequency interval. Then, we perform the DEP process and use the obtained frequencies (of spherical and ellipsoid models) for the alignment of the SWCNTs. Our empirical results declare the theo…
We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS$_2$ field effect transistors (FETs). The MoS$_2$ FETs are fabricated using a wafer-scale process on 8 $μ$m thick polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS$_2$ sheets, grown with different processes and showing different thicknesses, are analyzed and compared from the single device fabrication and characterization steps to the circuit level. The power detector prototypes exploit the nonlinearity of the transist…
High throughput experimental methods are known to accelerate the rate of research, development, and deployment of electronic materials. For example, thin films with lateral gradients in composition, thickness, or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect material properties under varying measurement conditions. Similarly, multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance. In this work, we apply…
The Organic Permeable Base Transistor (OPBT) is currently the fastest organic transistor with a transition frequency of 40 MHz. It relies on a thin aluminum base electrode to control the transistor current. This electrode is surrounded by a native oxide layer for passivation, currently created by oxidation in air. However, this process is not reliable and leads to large performance variations between samples, slow production and relatively high leakage currents. Here, we demonstrate for the first time that electrochemical anodization can be conveniently employed for the fabrication of high per…
A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of anti-ambipolar Ga…
Fabrication techniques such as laser patterning offer excellent potential for low cost and large area device fabrication. Conductive polymers can be used to replace expensive metallic inks such as silver and gold nanoparticles for printing technology. Electrical conductivity of the polymers can be improved by blending with carbon nanotubes. In this work, formulations of acid functionalised multiwall carbon nanotubes (f-MWCNT) and poly (ethylenedioxythiophene) [PEDOT]: polystyrene sulphonate [PSS] were processed, and thin films were prepared on plastic substrates. Conductivity of PEDOT: PSS inc…
Phase engineering of MoS2 transistors has recently been demonstrated and has led to record low contact resistances. The phase patterning of MoS2 flakes with laser radiation has also been realized via spectroscopic methods, which invites the potential of controlling the metallic and semiconducting phases of MoS2 transistors by simple light exposure. Nevertheless, the fabrication and demonstration of laser patterned MoS2 devices starting from the metallic polymorph has not been demonstrated yet. Here, we study the effects of laser radiation on 1T/1T'-MoS2 transistors with the prospect of driving…
In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance,…
Organic electrochemical transistors (OECTs) are currently being investigated for various applications, ranging from sensors to logics and neuromorphic hardware. The fabrication process must be compatible with flexible and scalable digital techniques to address this wide spectrum of applications. Here, we report a direct-write additive process to fabricate fully 3D printed OECTs. We developed 3D printable conducting, semiconducting, insulating, and electrolyte inks to achieve this. The 3D-printed OECTs, operating in the depletion mode, can be fabricated on thin and flexible substrates, yielding…
Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging from wearable electronics to smart packaging. Here we report high-performance MoS2 field-effect transistors on paper fabricated with a channel-array approach, combining the advantages of two large-area techniques: chemical vapor deposition and inkjet-printing.The first allows the pre-deposition of a pattern of MoS2; the second, the printing of dielectric lay…
Organic printed electronics has proven its potential as an essential enabler for applications related to healthcare, entertainment, energy and distributed intelligent objects. The possibility of exploiting solution-based and direct-writing production schemes further boosts the benefits offered by such technology, facilitating the implementation of cheap, conformable, bio-compatible electronic applications. The result shown in this work challenges the widespread assumption that such class of electronic devices is relegated to low-frequency operation, owing to the limited charge mobility of the …
Based on bottom-up assembly of highly variable neural cells units, the nervous system can reach unequalled level of performances with respect to standard materials and devices used in microelectronic. Reproducing these basic concepts in hardware could potentially revolutionize materials and device engineering which are used for information processing. Here, we present an innovative approach that relies on both iono-electronic materials and intrinsic device physics to show pattern classification out of a 12-unit bio-sensing array. We use the reservoir computing and learning concept to demonstra…
