Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA
Prasun Ghosal, Malabika Biswas, Manish Biswas
备注：
Journal of Telecommunications,Volume 1, Issue 1, pp113-117, February 2010
发表信息：
P. Ghosal, M. Biswas and M. Biswas, "Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA", Journal of Telecommunications, Volume 1, Issue 1, pp113-117, February 2010
Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely used in cryptography for securing the Internet traffic in modern day communication systems. The design of the digital cryptographic circuit was implemented in a Vertex 5 series (XCVLX5110T) target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of these algorithms, the proposed design was extensively simulated, synthesized for different FPGA devices both in Spartan and Virtex series from Xilinx viz. Spartan 3, Spartan 3AN, Virtex 5, Virtex E device families. The novelty and contribution of this work is in three folds: (i) Extensive simulation and synthesis of the proposed design targeted for various FPGA devices, (ii) Complete hardware implementation of encryption and decryption algorithms onto Virtex 5 series device (XCVLX5110T) based FPGA boards and, (iii) Generation of ICON and VIO core for the design and on chip verification and analyzing using Chipscope Pro. The experimental as well as implementation results compared to the implementations reported so far are quite encouraging.
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Nara Institute of Science and Technology（奈良先端科学技术大学院大学）；University of Information Technology（信息工程大学）；Vietnam National University（越南国立大学）；Le Quy Don Technical University（黎贵敦技术大学）
In this paper we will present various hardware architecture designs for implementing the SIMON 64/128 block cipher as a cryptographic component offering encryption, decryption and self-contained key-scheduling capabilities and discuss the issues and design options we encountered and the tradeoffs we made in implementing them. Finally, we will present the results of our hardware architectures' implementation performances on the Xilinx Spartan-6 FPGA series.
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