发表机构
Microelectronic Systems Design Research Group RPTU Kaiserslautern-Landau（RPTU凯泽斯劳滕-兰道微电子系统设计研究组）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究提出最全面的RISC-V HQC设计空间探索，基于可参数化架构框架评估29,920种配置，帕累托最优配置在FPGA上显著优于现有实现，降低LUT、延迟和块RAM使用。
AI 中文摘要
基于RISC-V的硬件/软件协同设计已成为在嵌入式设备上实现后量子密码学（PQC）的既定方法。其软件可编程性、可扩展的指令集架构以及可选的专用加速器创造了一个广阔的设计空间，提供了密码敏捷性和部署后更新所需的灵活性。对于HQC（一种被选为标准化的PQC密钥封装机制），已有多种基于RISC-V的实现被发布。然而，这些工作仅探索了该设计空间的一小部分。据我们所知，我们提出了最全面的基于RISC-V的HQC探索。我们的探索围绕一个新的、可参数化的架构框架展开，在该框架上，我们在FPGA上对所有三个HQC安全级别表征了29,920种不同的架构配置。该框架中的帕累托最优配置优于最先进的基于RISC-V的HQC实现，在延迟降低17%的情况下LUT利用率降低4.8倍，或在LUT利用率降低30%的情况下延迟降低69.6倍，同时所需块RAM最多减少10.6倍。
英文摘要
RISC-V-based hardware/software co-design has become an established methodology for implementing post-quantum cryptography (PQC) on embedded devices. Its software programmability, extensible instruction-set architecture, and optional dedicated accelerators create a broad design space that offers the flexibility required for crypto-agility and post-deployment updates. For HQC, a PQC key-encapsulation mechanism selected for standardization, several RISC-V-based implementations have already been published. However, these works explore only a small subset of this design space. We present, to the best of our knowledge, the most comprehensive exploration of RISC-V-based HQC. Our exploration is centered around a new, parametrizable architecture framework on which we characterize 29,920 distinct architectural configurations across all three HQC security levels on FPGA. The Pareto-optimal configurations from this framework outperform the state-of-the-art RISC-V-based HQC implementation, ranging from 4.8x lower LUT utilization at 17% lower latency to 69.6x lower latency at 30% lower LUT utilization, while also requiring up to 10.6x fewer block RAMs.
