信息隐藏中基于混沌迭代的伪随机数发生器的FPGA设计
FPGA Design for Pseudorandom Number Generator Based on Chaotic Iteration used in Information Hiding Application
摘要：
大量研究表明，随机数的低效生成是信息通信应用的一个重要瓶颈。因此，现场可编程门阵列（FPGA）被开发来处理一个可扩展的定点随机流生成方法。在我们以前的研究中，我们提出了一种技术，通过应用一些定义良好的离散混沌迭代，满足著名的Devaney的混沌定义，即混沌迭代（CI）。我们已经证明了具有CI的发生器能够产生合格的混沌随机数。本文针对FPGA器件对这种基于混沌迭代的发生器进行了优化设计。通过这样做，可以大大提高发电率。分析表明，这些硬件发生器也可以提供良好的统计混沌随机比特，也可以密码安全。最后给出了该算法在信息隐藏安全领域的应用实例。
英文摘要：
Lots of researches indicate that the inefficient generation of random numbers is a significant bottleneck for information communication applications. Therefore, Field Programmable Gate Array (FPGA) is developed to process a scalable fixed-point method for random streams generation. In our previous researches, we have proposed a technique by applying some well-defined discrete chaotic iterations that satisfy the reputed Devaney's definition of chaos, namely chaotic iterations (CI). We have formerly proven that the generator with CI can provide qualified chaotic random numbers. In this paper, this generator based on chaotic iterations is optimally redesigned for FPGA device. By doing so, the generation rate can be largely improved. Analyses show that these hardware generators can also provide good statistical chaotic random bits and can be cryptographically secure too. An application in the information hiding security field is finally given as an illustrative example.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
