Crypto-RV：面向物联网安全的高效FPGA-based RISC-V加密协处理器
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
AI总结：
Crypto-RV是一种基于FPGA的RISC-V加密协处理器，通过统一支持多种加密算法，实现高效、低功耗的物联网安全加密处理。
摘要：
加密操作对于保障物联网、边缘计算和自主系统至关重要。然而，当前的RISC-V平台缺乏对全面加密算法家族和后量子密码学的高效硬件支持。本文提出了Crypto-RV，一种RISC-V协处理器架构，它在一个64位数据路径中统一支持SHA-256、SHA-512、SM3、SHA3-256、SHAKE-128、SHAKE-256、AES-128、HARAKA-256和HARAKA-512。Crypto-RV引入了三个关键的架构创新：高带宽的内部缓冲区（128x64位）、专为加密设计的执行单元（四阶段流水线数据路径）以及具有自适应调度的双缓冲机制，优化了大哈希处理。在Xilinx ZCU102 FPGA上以160 MHz频率运行，动态功耗为0.851 W，Crypto-RV在基准RISC-V核心上实现了165到1,061倍的速度提升，在与强大CPU相比，能量效率提高了5.8到17.4倍。该设计仅占用34,704个LUTs、37,329个FFs和22个BRAMs，证明了其在资源受限的物联网环境中的可行性，适用于高性能、低功耗的加密处理。
英文摘要：
Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.
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