可重构架构上分区式环容错学习（RLWE）后量子密码的近阈值计算
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
AI总结：
针对基于FPGA的RLWE硬件加速器功耗较高的问题，提出按子组件关键路径分集群、为不同FPGA分区配置对应偏置电压的近阈值计算方案，有效降低功耗且资源占用和吞吐量更优。
摘要：
环容错学习（RLWE）算法应用于后量子密码（PQC）和同态加密（HE）算法中。现有经典密码算法可能在量子计算机面前被破解，攻击者可存储所有加密数据，一旦量子计算机投入使用，这些加密数据就可能被量子计算机破解，因此PQC算法是当前应用中的必要解决方案。另一方面，HE支持对加密数据进行运算，适用于在不泄露机密明文的前提下从第三方获取服务的场景。基于FPGA的RLWE这类PQC和HE硬件加速器，比基于处理器的平台及专用集成电路（ASIC）更具成本效益，但基于FPGA的硬件加速器相比ASIC设计功耗仍更高，近阈值计算（NTC）可能是基于FPGA实现RLWE的合适方案。本文实现了包含14个子组件的RLWE硬件加速器，基于所有14个子组件的关键路径构建集群，每个集群在拥有相同偏置电压$V_{ccint}$的FPGA分区中实现：关键路径更长的集群采用更高的Vccint以避免时序失效，关键路径更短的集群采用更低的偏置电压Vccint。这种电压缩放的分区式RLWE在Vivado和VTR平台上可分别节省约6%和约11%的功耗，所实现的RLWE硬件加速器的资源占用和吞吐量相比现有文献中的方案更优。
英文摘要：
Ring Learning With Error (RLWE) algorithm is used in Post Quantum Cryptography (PQC) and Homomorphic Encryption (HE) algorithm. The existing classical crypto algorithms may be broken in quantum computers. The adversaries can store all encrypted data. While the quantum computer will be available, these encrypted data can be exposed by the quantum computer. Therefore, the PQC algorithms are an essential solution in recent applications. On the other hand, the HE allows operations on encrypted data which is appropriate for getting services from third parties without revealing confidential plain-texts. The FPGA based PQC and HE hardware accelerators like RLWE is much cost-effective than processor based platform and Application Specific Integrated Circuit (ASIC). FPGA based hardware accelerators still consume more power compare to ASIC based design. Near Threshold Computation (NTC) may be a convenient solution for FPGA based RLWE implementation. In this paper, we have implemented RLWE hardware accelerator which has 14 subcomponents. This paper creates clusters based on the critical path of all 14 subcomponents. Each cluster is implemented in an FPGA partition which has the same biasing voltage $V_{ccint}$. The clusters that have higher critical paths use higher Vccint to avoid timing failure. The clusters have lower critical paths use lower biasing voltage Vccint. This voltage scaled, partitioned RLWE can save ~6% and ~11% power in Vivado and VTR platform respectively. The resource usage and throughput of the implemented RLWE hardware accelerator is comparatively better than existing literature.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
