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arXiv 0707.4233quant-ph
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时序可逆电路的综合

On the Synthesis of Sequential Reversible Circuit

Anindita Banerjee, Anirban Pathak

摘要:

用三种不同的逻辑方法给出了SR触发器、JK触发器、D触发器、T触发器、主从D触发器和主从JK触发器的可逆电路。所有的电路已经优化与现有的局部优化算法的帮助下(例如模板匹配,移动规则和删除规则)和优化的时序电路已与早期的建议相同。它已被证明,目前的建议有较低的门复杂度和较低的垃圾位的数量相比,早期的建议。还表明,通过引入新的门,在一些早期的建议中获得的门计数的优点是\textcolor{black}{artifact},如果允许,则每个电路块(除非有测量)可以减少到单个门。此外,它示出了一个可逆的触发器,甚至可以构建没有反馈。在这种情况下,一些重要的概念性问题有关的设计和优化的顺序可逆电路也得到了解决。

英文摘要:

Reversible circuits for SR flip flop, JK flip flop, D flip flop, T flip flop, Master Slave D flip flop and Master Slave JK flip flop have been provided with three different logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier proposals for the same. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of New gates is an \textcolor{black}{artifact} and if it is allowed then every circuit block (unless there is a measurement) can be reduced to a single gate. Further, it is shown that a reversible flip flop can be constructed even without a feedback. In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have also been addressed.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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