A clear protocol for synthesis of sequential reversible circuits from any particular gate library has been provided. Using that protocol, reversible circuits for SR latch, D latch, JK latch and T latch are designed from NCT gate library. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule). It has been shown that the present proposals have lower gate complexities, lower number of garbage bits, lower quantum cost and lower number of feedback loops compared to the earlier proposals. For a fair comparison, the optimized sequential circuits have been compared with the earlier proposals for the same after converting the earlier proposed circuits into equivalent NCT circuits. Further, we have shown that the advantage in gate count obtained in some of the earlier proposals by introduction of New gates is an artifact and if it is allowed then every reversible circuit block can be reduced to a single gate. In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have been addressed. A protocol for minimization of quantum cost of reversible circuit has also been proposed here.
Lund University（隆德大学）；University of Jyväskylä（于韦斯屈莱大学）；Technical University of Denmark（丹麦技术大学）；Korea Advanced Institute of Science and Technology (KAIST)（韩国科学技术院）
Security of Device-independent Quantum Key Distribution under Sequential Attack
S. N. Bose National Centre for Basic Sciences（S.N. 玻色基础科学国家中心）；Institute of Fundamental and Frontier Sciences, University of Electronic Science and Technology of China（电子科技大学前沿与基础科学学院）；Department of Physics and Center for Quantum Frontiers of Research and Technology (QFort), National Cheng Kung University（国立成功大学物理系及量子前沿研究与技术中心(QFort)）；Okinawa Institute of Science and Technology Graduate University（冲绳科学技术大学院大学）；Indian Institute of Technology Indore（印度理工学院印多尔分校）；Department of Physics, Hooghly Mohsin College（胡格利莫辛学院物理系）
