Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation.
We consider the test set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test set constructions for the standard stuck-at fault model as well as the usually intractable cell-fault model. We also give a practical test set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional ATPG.
Reversible computing has emerged as a possible low cost alternative to conventional computing in terms of speed, power consumption and computing capability. In order to achieve reliable circuits in reversible computing, provision for fault tolerance is necessary. A number of fault models, fault tolerant techniques (such as parity-preserving) and testing approaches have proposed in literature. This dissertation exploits parity-preserving characteristics of two reversible gates which provide low cost parity-preserving based fault tolerance. In order to extend online testability of reversible cir…
The reversible implementation of classical functions accounts for the bulk of most known quantum algorithms. As a result, a number of reversible circuit constructions over the Clifford+$T$ gate set have been developed in recent years which use both the state and phase spaces, or $X$ and $Z$ bases, to reduce circuit costs beyond what is possible at the strictly classical level. We study and generalize two particular classes of these constructions: relative phase circuits, including Giles and Selinger's multiply-controlled $iX$ gates and Maslov's $4$ qubit Toffoli gate, and measurement-assisted …
Detecting and isolating faults is crucial for synthesis of quantum circuits. Under the single fault assumption that is now routinely accepted in circuit fault analysis, we show that the behaviour of faulty quantum circuits can be fully characterized by the single faulty gate and the corresponding fault model. This allows us to efficiently determine test input states as well as measurement strategy that can be used to detect every single-gate fault using very few test cases and with minimal probability of error; in fact we demonstrate that most commonly used quantum gates can be isolated withou…
We present a quantum circuit synthesis algorithm for implementing universal fault-tolerant quantum computing based on concatenated codes. To realize fault-tolerant quantum computing, the fault-tolerant quantum protocols should be transformed into executable quantum circuits based on the nearest-neighbor interaction. Unlike topological codes that are defined based on local operations fundamentally, for the concatenated codes, it is possible to obtain the circuits composed of the local operations by applying the quantum circuit synthesis. However, by the existing quantum circuit synthesis develo…
We report optimal and asymptotically optimal reversible circuits composed of NOT, CNOT, and Toffoli (NCT) gates, keeping the count by the subsets of the gate types used. This study fine tunes the circuit complexity figures for the realization of reversible functions via reversible NCT circuits. An important consequence is a result on the limitation of the use of the $T$-count quantum circuit metric popular in applications.
The computational efficiency of quantum mechanics can be defined in terms of the qubit circuit model, which is characterized by a few simple properties: each computational gate is a reversible transformation in a connected matrix group; single wires carry quantum bits, i.e. states of a three-dimensional Bloch ball; states on two or more wires are uniquely determined by local measurement statistics and their correlations. In this paper, we ask whether other types of computation are possible if we relax one of those characteristics (and keep all others), namely, if we allow wires to be described…
We present a very general construction for quantum annealing protocols to solve Combinational Circuit Fault Diagnosis (CCFD) problems that restricts the evolution to the space of valid diagnoses. This is accomplished by using special local drivers that induce a transition graph on the space of feasible configurations that is regular and instance independent for each given circuit topology. Analysis of small instances shows that the energy gap has a generic form, and that the minimum gap occurs in the last third of the evolution. We used these features to construct an improved annealing schedul…
The work proposes an extension of the quantum circuit formalism where qubits (wires) are circular instead of linear. The left-to-right interpretation of a quantum circuit is replaced by a circular representation which allows to select the starting point and the direction in which gates are executed. The representation supports all the circuits obtained after computing cyclic permutations of an initial quantum gate list. Two circuits, where one has a gate list which is a cyclic permutation of the other, will implement different functions. The main question appears in the context of scalable qua…
In-situ benchmarking of fault-tolerant quantum circuits. I. Clifford circuits
Joint Center for Quantum Information and Computer Science, NIST/University of Maryland（量子信息与计算机联合中心，美国国家标准与技术研究院/马里兰大学）；Simons Institute for the Theory of Computing, University of California at Berkeley（西蒙斯计算理论研究所，加州大学伯克利分校）；Institute for Theoretical Physics, ETH Zürich（理论物理研究所，苏黎世联邦理工学院）；Department of Physics, Harvard University（物理学系，哈佛大学）；National Institute of Standards and Technology（美国国家标准与技术研究院）
The generation of reversible circuits from high-level code is an important problem in several application domains, including low-power electronics and quantum computing. Existing tools compile and optimize reversible circuits for various metrics, such as the overall circuit size or the total amount of space required to implement a given function reversibly. However, little effort has been spent on verifying the correctness of the results, an issue of particular importance in quantum computing. There, compilation allows not only mapping to hardware, but also the estimation of resources required…
In this paper we present a method for minimizing reversible quantum circuits using the Quantum Operator Form (QOF); a new representation of quantum circuit and of quantum-realized reversible circuits based on the CNOT, CV and CV$^\dagger$ quantum gates. The proposed form is a quantum extension to the well known Reed-Muller but unlike the Reed-Muller form, the QOF allows the usage of different quantum gates. Therefore QOF permits minimization of quantum circuits by using properties of different gates than only the multi-control Toffoli gates. We introduce a set of minimization rules and a pseud…
We develop a framework for resource efficient compilation of higher-level programs into lower-level reversible circuits. Our main focus is on optimizing the memory footprint of the resulting reversible networks. This is motivated by the limited availability of qubits for the foreseeable future. We apply three main techniques to keep the number of required qubits small when computing classical, irreversible computations by means of reversible networks: first, wherever possible we allow the compiler to make use of in-place functions to modify some of the variables. Second, an intermediate repres…
The failure susceptibility of the quantum hardware will force quantum computers to execute fault-tolerant quantum circuits. These circuits are based on quantum error correcting codes, and there is increasing evidence that one of the most practical choices is the surface code. Design methodologies of surface code based quantum circuits were focused on the layout of such circuits without emphasizing the reduced availability of hardware and its effect on the execution time. Circuit layout has not been investigated for practical scenarios, and the problem presented herein was neglected until now. …
Fault-tolerant quantum error correction is a necessity for any quantum architecture destined to tackle interesting, large-scale problems. Its theoretical formalism has been well founded for nearly two decades. However, we still do not have an appropriate compiler to produce a fault-tolerant, error corrected description from a higher level quantum circuit for state of the art hardware models. There are many technical hurdles, including dynamic circuit constructions that occur when constructing fault-tolerant circuits with commonly used error correcting codes. We introduce a package that convert…
In his 2003 paper "Towards an algebraic theory of Boolean circuits", Lafont notes that the class of reversible circuits over a set of k truth values is finitely generated when k is odd. He cites a private communication for the proof. The purpose of this short note is to make the content of that communication available.
Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimisation and execution of the expressed computations. However, the specification format makes it difficult to verify that optimised or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a deriv…
The design of time-independent local Hamiltonians that realise quantum algorithms is derived from the study of perfect state transfer. The novel features of this evolution are the perfect realisation of the computation, and the ability to implement operations in parallel rather than sequentially. This is applied to a quantum circuit for concatenated error correcting codes, and the properties of the eigenstates are compared to those of topological memories. An erroneous implementation of the algorithm (one where a single error could lead to a fault in the output) is found not to be topological,…
The efficient decomposition of multi-controlled gates is a significant factor in quantum compiling, both in circuit depth and T-gate count. Recent work has demonstrated that qudits have the potential to reduce resource requirements from linear to logarithmic depth and to avoid fractional phase rotations. Here we argue, based on the scaling of decoherence in high-index states, that circuit depth is not the primary factor, and that both the choice of entangling gate and interaction network topology act together to determine the spread of errors and ultimate failure rate in a circuit. We further …
