发表机构
Seoul National University; NextQuantum, Seoul National University（首尔大学; 首尔大学NextQuantum）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出一种基于故障等价重写的自动化方法，通过贝尔对缩减降低容错电路资源，并在Shor和Steane综合征提取中分别实现约21%和15%的逻辑错误率改进。
AI 中文摘要
我们提出了一种通过故障等价重写来自动缩减容错电路的方法。从已知的容错电路出发，该搜索应用非缩减的启用规则来暴露贝尔对缩减，每次缩减移除一个辅助态制备和一个CNOT门。由于每次搜索转换都保持故障等价性，所得电路继承了输入电路的容错性质。候选电路通过电路级蒙特卡罗模拟进行评估。对于使用$[[7,1,3]]$码的Shor风格综合征提取，我们的方法将一轮综合征测量从30次辅助态制备和54个CNOT门缩减至18次辅助态制备和42个CNOT门。在物理双量子比特错误率$p = 10^{-3}$下，优化后的电路将两种逻辑基态的逻辑错误率降低了约21%。在跨越两个数量级的$p$范围内，缩减幅度为13%至23%。我们还将该方法应用于基于Goto的已验证逻辑$\lvert 0 \rangle$制备构建的Steane动态综合征提取，其中验证量子比特用作标志。搜索选择了一个使用四个辅助量子比特和14个CNOT门的电路，与先前设计的资源数量相匹配，但CNOT深度有所改进。在$3p/10$的去极化空闲噪声下，所选电路将两种逻辑基态的逻辑错误率降低了约15%，在$p/10$下降低了约10%。这些结果表明，自动化的故障等价重写能够识别出具有更低资源成本或更好逻辑性能的电路，而无需单独验证每个候选电路的容错性。
英文摘要
We present an automated method for reducing fault-tolerant circuits through fault-equivalent rewrites. Starting from a known fault-tolerant circuit, the search applies non-reducing enabling rules to expose Bell-pair reductions, each of which removes an ancilla preparation and a CNOT gate. Because every search transition preserves fault equivalence, the resulting circuits inherit the fault-tolerance properties of the input circuit. Candidate circuits are evaluated using circuit-level Monte Carlo simulation. For Shor-style syndrome extraction with the $[[7,1,3]]$ code, our method reduces one syndrome-measurement round from 30 to 18 ancilla preparations and from 54 to 42 CNOT gates. At a physical two-qubit error rate of $p = 10^{-3}$, the optimized circuit lowers the logical error rate by approximately 21% for both logical basis states. The reduction ranges from 13% to 23% over a range of $p$ spanning two orders of magnitude. We also apply the method to Steane-based dynamic syndrome extraction constructed from Goto's verified logical-$\lvert 0 \rangle$ preparation, in which the verification qubit serves as a flag. The search selects a circuit using four ancillas and 14 CNOT gates, matching the resource counts of the previous design but with an improved CNOT depth. Under depolarizing idle noise at $3p/10$ the selected circuit lowers the logical error rate by approximately 15% for both logical basis states, and by approximately $10%$ at $p/10$. These results demonstrate that automated fault-equivalent rewriting can identify circuits with lower resource costs or improved logical performance without separately verifying the fault tolerance of every candidate.
