LEGEND, the Large Enriched Germanium Experiment for Neutrinoless $ββ$ Decay, is a ton-scale experimental program to search for neutrinoless double beta ($0νββ$) decay in the isotope $^{76}$Ge with an unprecedented sensitivity. Building on the success of the low-background $^{76}$Ge-based GERDA and MAJORANA DEMONSTRATOR experiments, the LEGEND collaboration is targeting a signal discovery sensitivity beyond $10^{28}\,$yr on the decay half-life with approximately $10\,\text{t}\cdot\text{yr}$ of exposure. Signal readout electronics in close proximity to the detectors plays a major role in maximizing the experiment's discovery sensitivity by reducing electronic noise and improving pulse shape analysis capabilities for the rejection of backgrounds. However, the proximity also poses unique challenges for the radiopurity of the electronics. Application-specific integrated circuit (ASIC) technology allows the implementation of the entire charge sensitive amplifier (CSA) into a single low-mass chip while improving the electronic noise and reducing the power consumption. In this work, we investigated the properties and electronic performance of a commercially available ASIC CSA, the XGLab CUBE preamplifier, together with a p-type point contact high-purity germanium detector. We show that low noise levels and excellent energy resolutions can be obtained with this readout. Moreover, we demonstrate the viability of pulse shape discrimination techniques for reducing background events.
A serializer ASIC and a VCSEL driver ASIC are needed for the front-end optical data transmission in the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed in a 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and consumed 843 mW and 320 mW, respectively. Based on a 130-nm CMOS technology, we design two pin-to-pin-compatible backup ASICs, LOCx2-130 and LOCld-130. Their power consumptions are much lower then of their counterparts, whereas other performance, such as the latency, data rate, and radiation toleran…
In this paper, we present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel transmitter ASIC for detector front-end readout. LOCx2-130 has two channels of encoders and serializers, and each channel operates at 4.8 Gbps. LOCx2-130 can interface with three types of ADCs, an ASIC ADC and two COTS ADCs. LOCx2-130 is fabricated in a commercial 130-nm CMOS technology and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a latency of less than 40.7 ns.
Three generations of full-custom analog integrated circuits designed for low-power, high-speed sampling of Radio-Frequency (RF) transients in excess of the Nyquist minimum have been developed. These 0.25$μm$ CMOS devices are denoted the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASICs and finally consist of 9 channels of 260 deep sampling. Continuous sampling is provided with common stop capability. Input analog bandwidth is approximately 1GHz and sampling speeds are adjustable from 0.02 to 3.7GSa/s. Completely parallel internal conversion supports 12-bit dig…
TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode front-end ASIC developed to readout the new inner tracking detector of the BESIII experiment, carried out at BEPCII in Beijing. The detector is planned to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM (Cylindrical Gas Electron Multiplier) with analog readout. The ASIC comprises 64 channels, each of which features a dual-branch architecture to extract and digitize the timestamp and charge of the input signal. The time-of-arrival is provided by a set of low-power TDCs, based on analog i…
We develop the vertex detector for the international linear collider (ILC) using the FPCCD (Fine Pixel CCD), whose pixel size is 5 x 5 um2. Together with the FPCCD sensor, a prototype of the readout ASIC was developed in 2008. The readout ASIC was confirmed to work correctly at slow readout speed (1.5 Mpix/sec). In this letter, we describe the status of the performance study for the readout ASIC.
In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.
High channel density and space restrictions required that the front end electronics integrated into the active elements of calorimeter. For that purpose novel readout chain base on Application-Specific Integrated Circuit (ASIC) designed for the Electromagnetic Calorimeter for the future International Linear Calorimeter experiment. In this paper, the performance study of ASIC with injected charge is presented.
The ATLAS experiment will replace the present Small Wheel (SW) detector with a New Small Wheel detector (NSW) aiming to improve the performance of muon triggering and precision tracking in the endcap region at the High-Luminosity LHC. Small-strip Thin Gap Chamber (sTGC) is one of the two new detector technologies used in this upgrade. A few custom-designed ASICs are needed for the sTGC detector. We designed an sTGC ASIC interface board to test ASIC-to-ASIC communication and validate the functionality of the entire system. A test platform with the final readout system is set up and the whole sT…
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge informatio…
One of candidates for the International Linear Collider(ILC)'s vertex detector is the Fine Pixel CCD (FPCCD) with a pixel size of 5 \times 5 (\mum^2). Sensor and readout systems are currently being studied and prototypes have been developed. In this paper we will report on the performance of latest developed readout ASIC prototype as well as the outline of the design strategy for the next ASIC prototype.
Multiple application-specific integrated circuits (ASIC) are required for the detectors if their readout channels are larger than that of ASIC channels. For a system with such a readout scheme, there is a need to configure channels among ASICs to achieve the lowest electronics noise and highest count rate. In this work, experiments were performed to investigate the performance of two different readout configurations between two ASICs in a cross-strip cadmium zinc telluride detector. A lower electronic noise level, better FWHM energy resolution performance, and higher count rate was found for t…
The next generation experiment in high energy particle physics will be International Linear Collider of electron and positron at the TeV scale. The experiment is aim to search the Higgs particle and to measure its properties. The physics program required the detector with high performance. One of the central detector is a Electromagnetic calorimeter, is going to measure the energy and position of high energy photons. Fine granularity and compactness brings to utilize the Si-W sampling detector. Due to high granularity the electromagnetic calorimeter will comprise of the order of $10^8$ readout…
The Large Enriched Germanium Experiment for Neutrinoless $ββ$ Decay (LEGEND) is a future ton-scale experimental program that will search for neutrinoless double beta decay ($0νββ$) in the isotope $^{76}$Ge with an unprecedented sensitivity. To achieve the projected discovery sensitivity at a half-life beyond $10^{28}\,$yr after about ten years of data taking, it is of utmost importance to operate in a background-free environment. This can be supported by using highly integrated readout electronics such as application-specific integrated circuit (ASIC) technology. In this work we investigated t…
Test beam results obtained with 3D pixel sensors bump-bonded to the RD53A prototype readout ASIC are reported. Sensors from FBK (Italy) and IMB-CNM (Spain) have been tested before and after proton-irradiation to an equivalent fluence of about $1$ $\times$ $10^{16}$ $\text{n}_{\text{eq}}$ cm$^{-2}$ (1 MeV equivalent neutrons). This is the first time that one single collecting electrode fine pitch 3D sensors are irradiated up to such fluence bump-bonded to a fine pitch ASIC. The preliminary analysis of the collected data shows no degradation on the hit detection efficiencies of the tested sensor…
We fabricated a readout ASIC with the fully depleted silicon-on-insulator (FD-SOI) technology for the pair-monitor. The pair-monitor is a silicon pixel device that measures the beam profile of the international linear collider. It utilizes the directional distribution of a large number of electron-positron pairs created by collision of bunches, and is required to tolerate radiation dose of about a few Mrad/year. The irradiation might cause the buried oxide layer of SOI to accumulate charges which interfere with intended functions. We thus performed extensive irradiation tests on the prototype …
The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 μm CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better …
Gotthard-II is a charge-integrating microstrip detector developed for experiments and diagnostics at free-electron lasers using hard X-rays of 5 keV - 20 keV. Thanks to its excellent single photon sensitivity, large dynamic range as well as high frame rate of 4.5 MHz in burst mode, its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), beam diagnostics, as well as veto signal generation for pixel detectors. The Gotthard-II ASIC has been designed and fabricated using UMC-110 nm technology. The final ASIC…
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measur…
In the large-scale high energy physics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics. This flow was successfully implemented in the development of the readout ASIC prototypes for the muon chambers of the CBM experiment. Th…
Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride (VFG CZT) detectors for gamma ray spectroscopy is presented. Corresponding to each ionizing event in the detector, the ASIC measures the amplitude and timing at the anode, the cathode and four pad sense electrodes associated with each sensor in a detector array. The ASIC is comprised of 52 channels of which there are 4 cathode channels and 48 channels which can…
The Large High Altitude Air Shower Observatory is in the R&D phase, in which the Water Cherenkov Detector Array is an important part. The signals of Photo-Multiplier Tubes would vary from single photo electron to 4000 photo electrons, and both high precision charge and time measurement is required. To simplify the signal processing chain, the charge-to-time conversion method is employed. A prototype of the front-end readout ASIC is designed and fabricated in Chartered 0.35 μm CMOS technology, which integrates time disctrimination and converts the input charge information to pulse widths. With …
A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The Adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the Adapter, has a FPGA-based reconfigurable logic and I/O interfaces, allowing users to choose various ASIC cards and Adapters for different types of det…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also prese…
A detector emulator method has been developed. It allows for testing any readout electronics with realistic detector-like signals under controlled conditions, beyond the limits of any experiment based on radiation sources. It can substitute for expensive test-beam campaigns, or predict their results. The detector emulator is a powerful tool for the engineering of detector concepts, with its capability to reproduce any detector signal feature to test the electronics response. Here, the method is applied to the case of the VMM3a ASIC tested with sTGC detector emulated signals. Measurements of ch…
The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier tubes (PMTs) scattered under water in an area of 80000 m2. As for the WCDA readout electronics, both high precision time and charge measurement is required over a large dynamic range from 1 photon electron (P.E.) to 4000 P.E. To reduce the electronics complexity and improve the system reliability, a readout scheme based on application specific integrated circui…
This writeup summarizes the work of the Topical Working Group 7 of the Instrumentation Frontier group of the Snowmass 2021 process. Group 'IF07' dealt with issues pertaining to ASICs and Readout Electronics. The community efforts as part of IF07 were organized across 7 white papers submitted to the Snowmass process and available in the arXiv.
A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference
Instituto Balseiro（巴尔塞罗研究所）；Instituto de Nanociencia y Nanotecnología INN (CNEA-CONICET)（纳米科学与技术研究所（CNEA-CONICET））；Fermi National Accelerator Laboratory（费米国家加速器实验室）；Universidad Nacional de Córdoba（科尔多瓦国立大学）；Comisión Nacional de Energía Atómica (CNEA)（国家原子能委员会）；CONICET（阿根廷国家科学研究委员会）
The aim of this work is to show the potential capabilities of monolithic crystals coupled to large SiPM arrays, to be considered as detector blocks for PET scanners enabling Time Of Flight (TOF) capabilities. Monolithic blocks allow one to decode the 3D photon impact position. This approach, along with TOF information, can be of high interest in clinical Positron emission tomography (PET) applications where a typical ring configuration is used. In this manuscript, we evaluate an ASIC- based readout for digitizing all signals coming from analog photosensors. Validation results with one-to-one c…
PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology, for photomultipliers array. It is a front-end electronics ASIC which allows triggerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R & D program, funded by French national agency for research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerl…
PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology [1], for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles [2] (ref.ANR-06-BLAN- 0186). The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC and a 24-bit Counter. The charge measurement should…
A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel…
We present the design and characterization of TIGER (Turin Integrated Gem Electronics for Readout), a 64-channel ASIC developed for the readout of the CGEM (Cylindrical Gas Electron Multiplier) detector, the proposed inner tracker for the 2018 upgrade of the BESIII experiment, carried out at BEPCII in Beijing. Each ASIC channel features a charge sensitive amplifier coupled to a dual-branch shaper stage, optimized for timing and charge measurement, followed by a mixed-mode back-end that extracts and digitizes the timestamp and charge of the input signals. The time-of-arrival is provided by a se…
We report on progress in the development of the LSTFE2 prototype front-end ASIC geared towards the readout of silicon microstrip sensors in a Linear Collider detector. We also discuss progress in the design of the back-end digital architecture for this readout scheme.
LEGEND (Large Enriched Germanium Experiment for Neutrinoless Double-Beta Decay) is a ton-scale experimental program to search for neutrinoless double beta ($0 νββ$) decay using high-purity germanium detectors enriched in the isotope $^{76}$Ge. An observation of $0 νββ$ decay would unequivocally prove the existence of lepton number violation and provide insight into the nature of neutrino masses. On-site construction for the first 200-kg phase (LEGEND-200) of the experiment will start at the Gran Sasso underground laboratory (Laboratory Nazionali del Gran Sasso, Italy) in mid-2020. In order to …
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most proba…
The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC)…
The FERS-5200 is the new CAEN Front-End Readout System for large detector arrays. It consists in a compact, distributed and easy-deployable solution integrating front-end based on ASICs, A/D conversion, data processing, synchronization and readout. Using the appropriate Front-End the solution perfectly fits a wide range of detectors such as SiPMs, multianode PMTs, GEMs, Silicon Strip detectors, Wire Chambers, Gas Tubes, etc. The first member of the FERS family is the unit A5202, a 64 channel readout card for SiPMs, based on the CITIROC ASIC by Weeroc SaS. The Concentrator board DT5215 can mana…
We present the design and the test results of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld65 for detector front-end readout. LOCld65 is designed in a commercial 65-nm CMOS technology with a power supply of 1.2 V. LOCld65 contains two separate channels with the same structure and the two channels share an I2C slave. Each channel consists of an input amplifier, four stages of limiting amplifiers (LAs), a high-current output driver, and a bias-current generator. In order to extend the bandwidth, the input amplifier uses an inductive peaking technique and the LAs…
We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout channels, and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9 e- +/- 11.3 e- (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons withi…
The readout electronics of the ATLAS Hadronic Endcap Calorimeter will have to withstand the about ten times larger radiation environment of the future high-luminosity LHC (HL-LHC) compared to their design values. The GaAs ASIC which comprises the heart of the readout electronics has been exposed to neutron and proton radiation with fluences up to ten times the total expected fluences for ten years of running of the HL-LHC. Neutron tests were performed at the NPI in Rez, Czech Republic, where a 36 MeV proton beam is directed on a thick heavy water target to produce neutrons. The proton irradiat…
IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35 microns process technology. Its power consumption is 800 micro watt per channel. The dynamic range of the ASIC can be extended to 1.1 MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7 micro seconds peak time. Spec…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $μ$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the S…
The main purpose of this work is to study the performance of the APV25 and VMM3a readout chips with regards to using them in the front-end readout system of a Triple-GEM detector. For the APV25, the Signal-to-Noise Ratio (SNR) was estimated with a cosmics measurement around 84.29 +/- 0.12. For the VMM3a, the noise of the chip was characterised in terms of the Equivalent Noise Charge (ENC) in the full parameter space and with increasing input capacitance. For the highest VMM gain and peaktime settings, the calculated ENC was about 300 electrons + 8 electrons/pF. Finally, a comparison was made b…
Calorimetry at future linear colliders could be based on a particle flow approach where granularity is the key to high jet energy resolution. Among different technologies, Micromegas chambers with 1 cm2 pad segmentation are studied for the active medium of a hadronic calorimeter. A chamber of 1 m2 with 9216 channels read out by a low noise front-end ASIC called MICROROC has recently been constructed and tested. Chamber design, ASIC circuitry and preliminary test beam results are reported.
We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. The total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-…
We constructed a gamma-ray detector by combining two types of scintillator array detectors with an MPPC array and evaluated the spectral performance by reading out the signals from the MPPC with a low-power integrated circuit (ASIC) manufactured by IDEAS in Norway. One of the two types of scintillators is a GAGG(Ce) (Ce-doped $ \rm{Gd_3Al_2Ga_3O_{12}}$) scintillator, and the other is an LFS scintillator. The scintillator array is 2.5 cm $\times$ 2.5 cm in size and is coated with $ \rm{BaSO_4}$-based white paint for GAGG(Ce) and an enhanced specular reflector (ESR) for LFS except for the side o…
