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arXiv 1902.05067cs.AR
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二进制表示的快速并行加法器

Fast Parallel Integer Adder in Binary Representation

Duggirala Meher Krishna, Duggirala Ravi

摘要:

二进制整数加法器是任何数字处理器的基本运算之一。为了将两个N位的整数相加,串行加法器需要尽可能多的时钟节拍。为了实现更高的速度,在文献中讨论了并联电路,并且这些电路通常在两个电平中操作。在较低级别,由较少比特数的块表示的整数被相加,并且在下一级别的级联级中,在先前加法运算中产生的进位被求和到被加数。本文描述了一种快速加法器的设计方法及其改进,第一种方法类似于归并排序算法的运算方法,分析和吸收了各步进位的一些重要性质,得到了一种在时间上与现有方法相当的并行加法器。在此之后,关键的见解在改进的设计中得以实现,该设计需要2个时钟节拍来执行加法运算,只需要O(square(N))空间。比特数N通常被选择为2的正整数幂。加速是通过用于2的i次幂的增量运算的专用电路来实现的,对于i = 0,1,.,N-1,每个操作只需要一个时钟滴答完成。讨论了该加法器在乘法运算中的实用性。标准乘法方法利用量化器和3位到2位合并电路来产生整数,该整数以二进制表示与2的非负整数幂的位置(加权系数)相对应的列中的1的数目。最后两个合并的整数在最后由加法器相加。

英文摘要:

An integer adder for integers in the binary representation is one of the basic operations of any digital processor. For adding two integers of N bits each, the serial adder takes as many clock ticks. For achieving higher speeds, parallel circuits are discussed in the literature, and these circuits usually operate in two levels. At the lower level, integers represented by blocks of smaller number of bits are added, and in a cascade of stages in the next level, the carries produced in previous addition operations are summed to the augends. In this paper, we describe a fast method and an improvement of it. The first attempt resembles the operation method of the merge sort algorithm, from which some important properties of carries produced in each stage are analysed and assimilated, resulting in a parallel adder that runs in time comparable to the existing methods. After that, the crucial insights are brought to fruition in an improved design, which takes 2 clock ticks to perform the addition operation requiring only O(square(N)) space. The number of bits N is chosen usually to be a positive integer power of 2. The speedup is achieved by special purpose circuits for increment operations by i-th power of 2 , for i = 0, 1, ..., N-1, each operation taking only a single clock tick to complete. The usefulness of this adder for multiplication operation is discussed. The standard multiplication method utilizes quantizer and 3-bit to 2-bit consolidation circuits to produce an integer that represents in binary the number of 1s in a column corresponding to a place (weighted coefficient) of nonnegative integer power of 2. The last two consolidated integers are added by an adder in the end.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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