面向大规模并行处理的可重构多操作数加法器设计
Design of Reconfigurable Multi-Operand Adder for Massively Parallel Processing
摘要：
本文提出了一种用于深度学习系统的可重构组合多操作数加法器的系统研究和实现。进位的大小随着操作数的变化而变化，因此需要一种可靠的算法来估计进位位的确切数目，以优化实现可重构多操作数加法器。与使用两个操作数加法器的顺序实现相比，组合多操作数加法器可以更快。这种加法器的用例出现在深度神经网络的现代处理器中。这样的处理器需要在芯片上大规模并行计算资源。本文提出了一种估计进位大小上界的方法。一种计算多操作数加法运算所需进位位的精确数目的方法。提出了一种快速组合并行4操作数加法器模块。还描述了一种算法来重新配置这些加法器模块，以实现更大的加法器。此外，本文提出了两个紧凑但较慢的迭代结构，实现多操作数加法，每次迭代一列，直到覆盖整个字。这种串行/迭代操作是缓慢的，但占用小的空间，而并行操作是快速的，但使用大的芯片上的硅面积。有趣的是，两种架构的面积与吞吐量之比可以倾向于更慢，更小和更大数量的单元，而不是更少数量的快速和大型计算单元。文中提出的一个引理可以用来确定这种倾斜发生的条件。潜在地，这可以节省硅空间并增加用于高性能计算的芯片的吞吐量。给出了一个16操作数加法器和一组用于神经网络的4操作数加法器的模拟结果。仿真结果表明，性能增益提高的操作或操作数的数量增加。
英文摘要：
The paper presents a systematic study and implementation of a reconfigurable combinatorial multi-operand adder for use in Deep Learning systems. The size of carry changes with the number of operands and hence a reliable algorithm to estimate exact number of carry bits is needed for optimal implementation of a reconfigurable multi-operand adder. A combinatorial multi-operand adder can be faster compared to a sequential implementation using a two operand adder. Use cases for such adders occur in modern processors for deep neural networks. Such processors require massively parallel computing resources on chip. This paper presents a method to estimate the upper bound on the size of carry. A method to compute the exact number of carry bits required for a multi-operand addition operation. A fast combinatorial parallel 4-operand adder module is presented. An algorithm to reconfigure these adder modules to implement larger adders is also described. Further, the paper presents two compact but slower iterative structures that implement multi-operand addition, iterating with one column at a time till the entire word is covered. Such serial/iterative operations are slow but occupy small space while parallel operations are fast but use large silicon area on chip. Interestingly, the area-to-throughput ratio of two architectures can tilt in favor of slower, smaller and large number units instead of the fewer numbers of fast and large compute units. A lemma presented in the paper may be used to identify the condition when such tilt occurs. Potentially, this can save silicon space and increase the throughput of chips for high performance computing. Simulation results of a 16 operand adder and using an set of 4-operand adders for use in neural networks have been presented. Simulation results show that performance gain improves as the number of operations or operands increases.
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