无电平转换器CSA设计中基于行的双位数分配及其近阈值操作
Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation
摘要：
亚阈值电路设计在一些超低功耗应用中非常流行，其中最小能耗是主要关注的问题。但是，由于驱动电流较弱，这些电路通常会遭受巨大的性能下降。因此，本文主要针对一种近阈值电路（NTC）的性能进行分析，该电路在保留亚阈值设计的优良能效的同时，又在一定程度上提高了性能。一种改进的基于行的双通道4操作数CSA（进位保存加法器）的设计已报告在目前的工作中使用45纳米技术。此外，为了了解四操作数CSA设计的近阈值操作的有效性，将其与其他设计风格进行了比较。从针对20 MHz的频率获得的仿真结果，我们发现所提出的CSA设计方案消耗3.009*10-7瓦的平均功率（Pavg），这比常规CSA设计的平均功率几乎小90.9%。然而，从输出端最大延迟的角度来看，与亚阈值CSA设计相比，CSA设计的建议方案提供了44.37%的改善。
英文摘要：
Subthreshold circuit designs are very much popular for some of the ultra low power applications, where the minimum energy consumption is the primary concern. But, due to the weak driving current, these circuits generally suffer from huge performance degradation. Therefore, in this paper, we primarily targeted to analyze the performance of a Near-Threshold Circuit (NTC), which retains the excellent energy efficiency of the subthreshold design, while improving the performance to a certain extent. A modified row-based dual Vdd 4-operand CSA (Carry Save Adder) design has been reported in the present work using 45 nm technology. Moreover, to find out the effectiveness of the near-threshold operation of the 4-operand CSA design; it has been compared with the other design styles. From the simulation results, obtained for the frequency of 20 MHz, we found that the proposed scheme of CSA design consumes 3.009*10-7 Watt of Average Power (Pavg), which is almost 90.9 % lesser than that of the conventional CSA design. Whereas, looking at the perspective of maximum delay at output, the proposed scheme of CSA design provides a fair 44.37 % improvement, compared to that of the subthreshold CSA design.
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