二维离散四元数傅里叶变换处理器中四元数乘法单元的硬件高效方案
Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors
摘要：
在本文中，我们提供并讨论了三个有效的结构解决方案，面向硬件实现的离散四元数傅立叶变换的基本操作，降低了实现复杂性。第一个解决方案：一种用于计算SQ乘积的方案，第二种方案：一种用于计算QT乘积的方案，以及第三种方案：一种用于计算SQT乘积的方案，其中S是所谓的I-四元数，T是J-四元数，以及Q是通常的四元数。两个常用四元数的直接乘法需要16个实数乘法（或在完全并行硬件实现的情况下的两个操作数乘法器）和12个实数加法（或二进制加法器）。同时，我们的解决方案允许设计的计算单元，它只消耗6个乘法器加6个两个输入加法器的实施平方或qt的基本操作和9个二进制乘法器加6个两个输入加法器和4个四输入加法器的实施平方基本操作。
英文摘要：
In this paper, we offer and discuss three efficient structural solutions for the hardware-oriented implementation of discrete quaternion Fourier transform basic operations with reduced implementation complexities. The first solution: a scheme for calculating sq product, the second solution: a scheme for calculating qt product, and the third solution: a scheme for calculating sqt product, where s is a so-called i-quaternion, t is an j-quaternion, and q is an usual quaternion. The direct multiplication of two usual quaternions requires 16 real multiplications (or two-operand multipliers in the case of fully parallel hardware implementation) and 12 real additions (or binary adders). At the same time, our solutions allow to design the computation units, which consume only 6 multipliers plus 6 two input adders for implementation of sq or qt basic operations and 9 binary multipliers plus 6 two-input adders and 4 four-input adders for implementation of sqt basic operation.
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