四进制串并加法器的设计与分析
On the Design and Analysis of Quaternary Serial and Parallel Adders
摘要：
为了减少加法器电路的时间和面积，多年来人们对加法器电路的优化技术进行了广泛的研究，主要是在二进制逻辑系统中。本文给出了在四值逻辑系统中设计一个全加器所需的公式。推导了单级并行加法器作为先行进位加法器的计算公式。我们还设计了一个对数级并行加法器，它可以在log2（n）时间延迟内计算n个量子位的进位。最后，我们比较了这些设计，最后提出了一种混合加法器，它结合了串行和并行加法器的优点。
英文摘要：
Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
