一种行并行的8 $\times$ 8二维DCT结构及其基于代数的精确计算
A Row-parallel 8$\times$8 2-D DCT Architecture Using Algebraic Integer Based Exact Computation
摘要：
提出了一种基于代数整数（AI）的时间复用行并行结构和两种最终重构步（FRS）算法，用于实现二元AI编码的二维离散余弦变换（DCT）。该结构直接实现了一个无误差的2-D DCT，而不需要在行-列变换之间使用FRS，从而导致8 $\times$ 8 2-D DCT，这是完全没有量化误差的AI基础。因此，FRS中每个系数的用户可选择的精度便于64个系数中的每个系数独立于其他系数设置其精度，避免了通道之间的量化噪声泄漏，这是公开的DCT设计的情况。所提出的FRS使用基于（i）优化的Dempster-Macleod乘数和（ii）扩展因子缩放的两种方法。这种架构使低噪声高动态范围的数字视频处理，需要完全控制的2-D DCT的有限精度计算的应用。所提出的架构和FRS技术进行了实验验证和验证，使用硬件实现的物理实现和FPGA芯片上验证。六个设计，4位和8位输入字的大小，使用两个建议的FRS计划，已设计，模拟，物理实现和测量。在8位输入设计中实现的最大时钟速率和块速率分别为307.787 MHz和38.47 MHz，这意味着如果最终嵌入到实时视频处理系统中，像素速率为8 $\times$ 307.787 $\approx$ 2.462 GHz。对于1920 $\times$ 1080的图像尺寸，等效帧速率约为1187.35 Hz。所有实现都在Xilinx Virtex-6 XC6VLX240T FPGA器件上运行。
英文摘要：
An algebraic integer (AI) based time-multiplexed row-parallel architecture and two final-reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8$\times$8 2-D DCT which is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on (i) optimized Dempster-Macleod multipliers and (ii) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on FPGA chip. Six designs, for 4- and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented and measured. The maximum clock rate and block-rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8$\times$307.787$\approx$2.462 GHz if eventually embedded in a real-time video-processing system. The equivalent frame rate is about 1187.35 Hz for the image size of 1920$\times$1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
