一种基于查找表的二进制编码十进制加法器设计
A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design
摘要：
BCD码（Binary Coded Decimal）是计算和电子通信中普遍采用的一种精度高、易于转换、可读的表示法，本文提出了一种树型结构的并行BCD码加法算法，该算法降低了算法的时间复杂度。由于FPGA（现场可编程门阵列）技术的诸多优点和应用，BCD加法器采用基于查找表（LUT）的设计会更有效。本文的主要贡献是提出了一种最小尺寸和最小深度的基于LUT的BCD加法器电路结构。
英文摘要：
The BCD (Binary Coded Decimal) being the more accurate and human-readable representation with ease of conversion, is prevailing in the computing and electronic communication.In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity. BCD adder is more effective with a LUT (Look-Up Table)-based design, due to FPGA (Field Programmable Gate Array) technology's enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
