关于逻辑电路中多位翻转的可能性
On the likelihood of multiple bit upsets in logic circuits
摘要：
在纳米技术中，软错误对电路的可靠性有显著的影响。在架构级别，软错误通常由概率位翻转模型来建模。在开发这种抽象故障模型时，要考虑的一个重要问题是由粒子撞击引起的多个比特错误的可能性。这种可能性在存储器中已经得到了很大程度的研究，但在逻辑电路中还没有得到同样程度的理解。在本文中，我们试图量化的可能性，一个单一的瞬态事件可能会导致多个位错误的组合门和触发器组成的逻辑电路。特别是，我们计算的条件概率的多个位翻转给定的一个单一的位翻转的瞬态的结果。为了计算这个条件概率，我们使用蒙特卡罗技术，其中使用详细的布局后电路模拟生成的样本。我们在ISCAS'85基准测试和一些其他电路上的实验表明，这个条件概率是相当显著的，可以高达0.31。因此，我们得出结论，必须考虑多个位翻转，以获得一个现实的软错误的架构故障模型。
英文摘要：
Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the architectural level, soft errors are commonly modeled by a probabilistic bit-flip model. In developing such abstract fault models, an important issue to consider is the likelihood of multiple bit errors caused by particle strikes. This likelihood has been studied to a great extent in memories, but has not been understood to the same extent in logic circuits. In this paper, we attempt to quantify the likelihood that a single transient event can cause multiple bit errors in logic circuits consisting of combinational gates and flip-flops. In particular, we calculate the conditional probability of multiple bit-flips given that a single bit flips as a result of the transient. To calculate this conditional probability, we use a Monte Carlo technique in which samples are generated using detailed post-layout circuit simulations. Our experiments on the ISCAS'85 benchmarks and a few other circuits indicate that, this conditional probability is quite significant and can be as high as 0.31. Thus we conclude that multiple bit-flips must necessarily be considered in order to obtain a realistic architectural fault model for soft errors.
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