中子感生撞击：关于逻辑电路中多次位翻转的可能性
Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits
摘要：
来自宇宙射线或包装材料的高能粒子可在逻辑电路中产生毛刺或电流瞬变（单粒子瞬变或SET）。该SET最终会被寄存器捕获，导致寄存器内容翻转，这被称为软错误或单粒子翻转（SEU）。软错误通常被建模为概率性单个比特翻转模型。在开发这种抽象故障模型时，要考虑的一个重要问题是由粒子撞击引起的多个比特错误的可能性。在文献中注意到SET导致多次翻转的事实。我们进行了表征研究的影响，一个设置上的逻辑电路，以量化的程度，设置可以导致多位翻转。我们使用后布局电路模拟和蒙特卡罗抽样方案，以获得准确的位翻转统计。我们在ISCAS'85，ISCAS'89和ITC'99基准在180纳米和65纳米技术进行模拟。我们发现，相当一部分的SEU结果有多个寄存器翻转。我们进一步分析了罢工的寄存器和罢工的逻辑门，多个翻转的个人贡献。我们发现，在错误的结果中，“门罢工”情况下多次位翻转的概率很大，高达50%，而“寄存器罢工”情况下的概率仅为2%左右。这意味着，原则上，我们可以使用强化触发器设计消除由于寄存器撞击而导致的触发。然而，在这样的设计中，在由于浇口撞击而产生的剩余翻转中，很大一部分可能是多次翻转。
英文摘要：
High energy particles from cosmic rays or packaging materials can generate a glitch or a current transient (single event transient or SET) in a logic circuit. This SET can eventually get captured in a register resulting in a flip of the register content, which is known as soft error or single-event upset (SEU). A soft error is typically modeled as a probabilistic single bit-flip model. In developing such abstract fault models, an important issue to consider is the likelihood of multiple bit errors caused by particle strikes. The fact that an SET causes multiple flips is noted in the literature. We perform a characterization study of the impact of an SET on a logic circuit to quantify the extent to which an SET can cause multiple bit flips. We use post-layout circuit simulations and Monte Carlo sampling scheme to get accurate bit-flip statistics. We perform our simulations on ISCAS'85, ISCAS'89 and ITC'99 benchmarks in 180nm and 65nm technologies. We find that a substantial fraction of SEU outcomes had multiple register flips. We futher analyse the individual contributions of the strike on a register and the strike on a logic gate, to multiple flips. We find that, amongst the erroneous outcomes, the probability of multiple bit-flips for 'gate-strike' cases was substantial and went up to 50%, where as those for 'register-strike' cases was just about 2%. This implies that, in principle, we can eliminate the flips due to register strikes using hardened flip-flop designs. However, in such designs, out of the remaining flips which will be due to gate strikes, a large fraction is likely to be multiple flips.
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