CLEAR：架构弹性的跨层探索-结合硬件和软件技术以容忍处理器内核中的软错误
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores
摘要：
我们提出了第一种框架，它克服了一个主要的挑战，在设计的数字系统，是弹性可靠性故障：实现所需的弹性目标，以最小的成本（能源，电力，执行时间，面积），通过结合弹性技术在各个层次的系统堆栈（电路，逻辑，架构，软件，算法）。这也被称为跨层弹性。在本文中，我们专注于辐射引起的处理器核的软错误。我们解决单粒子翻转（SEU）和单粒子多重翻转（SEMU）在陆地环境中。我们的框架自动和系统地探索了大空间的综合弹性技术及其组合跨系统堆栈的各个层（本文中的586个跨层组合），得出了具有成本效益的解决方案，以最小的成本实现弹性目标，并为新的弹性技术的设计提供了指导方针。我们证明了我们的框架的实用性和有效性，使用两种不同的设计：一个简单的，有序的处理器核心和一个复杂的，无序的处理器核心。我们的研究结果表明，精心优化的电路级加固，逻辑级奇偶校验和微架构恢复的组合提供了一个高成本效益的软错误弹性解决方案的通用处理器内核。例如，对于无序内核，仅以2.1%的能源成本（对于有序内核为6.1%）实现了静默数据损坏率的50倍改进，而没有速度影响。然而，在对软错误对应用程序基准测试的影响进行全面分析的指导下，选择性电路级加固也提供了一种具有成本效益的软错误恢复解决方案（静默数据损坏率提高50倍，额外的能源成本约为1%）。
英文摘要：
We present a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). This is also referred to as cross-layer resilience. In this paper, we focus on radiation-induced soft errors in processor cores. We address both single-event upsets (SEUs) and single-event multiple upsets (SEMUs) in terrestrial environments. Our framework automatically and systematically explores the large space of comprehensive resilience techniques and their combinations across various layers of the system stack (586 cross-layer combinations in this paper), derives cost-effective solutions that achieve resilience targets at minimal costs, and provides guidelines for the design of new resilience techniques. We demonstrate the practicality and effectiveness of our framework using two diverse designs: a simple, in-order processor core and a complex, out-of-order processor core. Our results demonstrate that a carefully optimized combination of circuit-level hardening, logic-level parity checking, and micro-architectural recovery provides a highly cost-effective soft error resilience solution for general-purpose processor cores. For example, a 50x improvement in silent data corruption rate is achieved at only 2.1% energy cost for an out-of-order core (6.1% for an in-order core) with no speed impact. However, selective circuit-level hardening alone, guided by a thorough analysis of the effects of soft errors on application benchmarks, provides a cost-effective soft error resilience solution as well (with ~1% additional energy cost for a 50x improvement in silent data corruption rate).
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
