qBSA：32位块偏斜RSFQ算术逻辑单元的逻辑设计
qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit
摘要：
单通量量子（SFQ）电路是一种极具吸引力的超CMOS技术，因为它们承诺在超过25 GHz的时钟频率下将功耗降低两个数量级。然而，每个SFQ门都是时钟控制的，从而产生非常深的门级流水线，难以保持完整，特别是对于包含数据相关操作的序列。本文提出了通过重新设计数据路径来增加SFQ流水线的吞吐量，以在比更高有效位更早的时钟周期上接受和操作最低有效位（LSB）。这种偏斜的数据路径方法减少了LSB侧的延迟，这可以更早地被反馈以用于随后的数据相关操作，从而增加其吞吐量。特别地，我们建议将位分组为并发操作的4位块，并为32位操作创建块偏斜数据路径单元。这种偏斜方法允许在第一个4位块完成后立即开始后续的数据相关操作。利用这种通用方法，我们开发了一个块偏斜MIPS兼容的32位ALU。我们的门级Verilog设计提高了2x和1.5x的吞吐量的32位数据相关的操作相比，以前提出的4位片和32位Ladner-Fischer ALU分别。
英文摘要：
Single flux quantum (SFQ) circuits are an attractive beyond-CMOS technology because they promise two orders of magnitude lower power at clock frequencies exceeding 25 GHz.However, every SFQ gate is clocked creating very deep gate-level pipelines that are difficult to keep full, particularly for sequences that include data-dependent operations. This paper proposes to increase the throughput of SFQ pipelines by re-designing the datapath to accept and operate on least-significant bits (LSBs) clock cycles earlier than more significant bits. This skewed datapath approach reduces the latency of the LSB side which can be feedback earlier for use in subsequent data-dependent operations increasing their throughput. In particular,we propose to group the bits into 4-bit blocks that are operatedon concurrently and create block-skewed datapath units for 32-bit operation. This skewed approach allows a subsequent data-dependent operation to start evaluating as soon as the first 4-bit block completes. Using this general approach, we developa block-skewed MIPS-compatible 32-bit ALU. Our gate-level Verilog design improves the throughput of 32-bit data dependent operations by 2x and 1.5x compared to previously proposed 4-bit bit-slice and 32-bit Ladner-Fischer ALUs respectively.
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