The effects of an atomistic interface roughness in n-type silicon nanowire transistors (SiNWT) on the radio frequency performance are analyzed. Interface roughness scattering (IRS) is statistically investigated through a three dimensional full-band quantum transport simulation based on the sp3d5s?* tight-binding model. As the diameter of the SiNWT is scaled down below 3 nm, IRS causes a significant reduction of the cut-off frequency. The fluctuations of the conduction band edge due to the rough surface lead to a reflection of electrons through mode-mismatch. This effect reduces the velocity of electrons and hence the transconductance considerably causing a cut-off frequency reduction.
Experimental observation of highly reduced thermal conductivity in surface-roughness dominated silicon nanowires have generated renewed interest in low-dimensional thermoelectric devices. Using a previous work where the scattering of phonons from a rough surface is mapped to scattering from randomly situated localized phonons in the bulk of a smooth nanowire, we consider the thermal current across a nanowire for various strengths of surface disorder. We use non-equilibrium Green's function techniques that allow us to evaluate the thermal current beyond the linear response regime, for arbitrary…
We present detailed Raman studies of graphene deposited on gallium nitride nanowires with different variations in height. Our results show that different density and height of nanowires being in contact with graphene impact graphene properties like roughness, strain and carrier concentration as well as density and type of induced defects. Detailed analysis of Raman spectra of graphene deposited on different nanowire substrates shows that bigger differences in nanowires height increase graphene strain, while higher number of nanowires in contact with graphene locally reduce the strain. Moreover…
Performance Evaluation of Ballistic Silicon Nanowire Transistors with Atomic-basis Dispersion Relations
在这封信中，我们探讨了能带结构对弹道硅纳米线晶体管（SNWT）性能的影响。用sp 3d 5s * 紧束缚模型计算了硅纳米线的能量色散关系。基于计算的色散关系，弹道电流的n型和p型SNWT的评估通过使用半数值弹道模型。对于大直径的纳米线，我们发现，弹道p-SNWT提供一半的弹道n-SNWT的ON电流。然而，对于小直径，p型SNWT的导通电流接近其n型对应物。最后，SNWTs的载流子注入速度与平面金属氧化物半导体场效应晶体管进行了比较，清楚地表明了量子限制对SNWTs性能极限的影响。
Studies of possible localization of phonons in nanomaterials have gained importance in recent years in the context of thermoelectricity where phonon-localization can reduce thermal conductivity, thereby improving the efficiency of thermoelectric devices. However, despite significant efforts, phonon-localization has not yet been observed experimentally in real materials. Here we propose that surface-roughness dominated nanowires are ideal candidates to observe localization of phonons, and show numerically that the space and time evolution of the energy generated by a heat-pulse injected at a gi…
We analyze, both theoretically and numerically, the temperature dependent thermal conductivity \k{appa} of two-dimensional nanowires with surface roughness. Although each sample is characterized by three independent parameters - the diameter (width) of the wire, the correlation length and strength of the surface corrugation - our theory predicts that there exists a universal regime where \k{appa} is a function of a single combination of all three model parameters. Numerical simulations of propagation of acoustic phonons across thin wires confirm this universality and predict a d 1/2 dependence…
We report the operation of a field-effect transistor based on a single InAs nanowire gated by an ionic liquid. Liquid gating yields very efficient carrier modulation with a transconductance value thirty time larger than standard back gating with the SiO2 /Si++ substrate. Thanks to this wide modulation we show the controlled evolution from semiconductor to metallic-like behavior in the nanowire. This work provides the first systematic study of ionic-liquid gating in electronic devices based on individual III-V semiconductor nanowires: we argue this architecture opens the way to a wide range of …
Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors
理解和模拟纳米线晶体管性能极限的能力是设计下一代器件的关键。在这里，我们报告的高迁移率结无栅全包围纳米线场效应晶体管的载流子迁移率在室温下达到2000 cm 2/V.s的研究。依赖于温度的运输测量揭示了激活运输在低温下由于表面捐助者，而在室温下的运输表现出扩散行为。从电导率数据中，提取的值的声速在InAs纳米线被发现是一个顺序小于散装。这种低声速归因于普遍出现在这些纳米线中的扩展的晶体缺陷。分析温度相关的迁移率数据，我们确定了关键的散射机制限制在这些纳米线的载流子传输。最后，使用这些散射模型，我们进行漂移扩散的纳米线场效应晶体管的输运模拟和比较与实验测量的设备性能。我们的器件建模提供了深入了解InAs纳米线晶体管的性能限制，并可用作基于MEMS的集成电路的预测方法。
3D full-band, Atomistic Quantum transport in n-Si Junction less Nanowire field-effect transistors
在本工作中，我们使用三维全带原子sp 3d 5s自旋轨道耦合紧束缚方法研究了n-Si无结纳米线场效应晶体管中的量子输运。本文研究了无n-Si结纳米线场效应晶体管的IDSVGS传输特性、IDSVDS输出特性、导通漏电流、截止漏电流、亚阈值摆幅和能量位置分辨电子密度谱Gnx，E。我们还研究了IDS VGS传输特性与高K栅材料的变化。基于非平衡格林函数方法，自洽地求解耦合Poisson Schr“odinger方程，对n-Si无结纳米线场效应晶体管中的电势和局域态密度进行了量子力学模拟.
Giant thermovoltage in single InAs-nanowire field-effect transistors
毫伏范围的热电压证明在单一的InAs纳米线的场效应晶体管。由于埋入式加热方案，我们驱动大的热偏压DT> 10 K和纳米结构上的电导的强场效应调制。这使得精确映射的Seebeck系数S的演变作为室温和100 K $之间的门控电导率的函数。基于这些实验数据的电子迁移率的一个新的估计。这个值进行了比较，与标准的场效应为基础的迁移率估计的结果和讨论有关的设备中的电荷陷阱的效果。
Universal features of phonon transport in nanowires with correlated surface roughness
在有意粗糙化的硅纳米线（SiNW）中实验观察到的超低热导率$κ$在声子蒙特卡罗模拟中再现，其中指数相关的真实空间粗糙表面类似于测量[J.Lim，K. Hippalgaonkar，S. C. Andrews，A. Majumdar和P. Yang，Nano Lett. 12，2475（2012）]。通用功能的热输运揭示$κ$作为一个功能的归一化几何平均自由程$\barλ$（$0<\barλ<1$）的扩散（Casimir）限制对应于$\barλ=1/2$。$κ$与$\barλ$在低至中等粗糙度（高$\barλ$）下呈指数关系，其中内部散射随机中断声子在SiNW上的反弹，而在高粗糙度（低$\barλ$）下呈线性关系，其中同一表面处的多次散射事件导致超低的非晶极限热导率。
Atomistic quantum transport simulation of realistically large devices is computationally very demanding. The widely used mode space (MS) approach can significantly reduce the numerical cost but good MS basis is usually very hard to obtain for atomistic full-band models. In this work, a robust and parallel algorithm is developed to optimize the MS basis for atomistic nanowires. This enables tight binding non-equilibrium Green's function (NEGF) simulation of nanowire MOSFET with realistic cross section of $\rm 10nm\times10nm$ using a small computer cluster. This approach is applied to compare th…
Simulations of Nanowire Transistors: Atomistic vs. Effective Mass Models
采用10轨道sp 3d 5s * 原子紧束缚模型描述纳米线晶体管的电子结构，采用势垒顶半经典弹道模型计算纳米线晶体管的输运性质，研究了纳米线晶体管中电子输运的弹道性能.色散是自洽计算的二维泊松解的静电势的截面的导线。在强量子化下，纳米线的有效质量从体值显著变化，并且谷分裂等效应强烈地提升了谷的简并性。这些效应在用电荷填充晶格的情况下甚至更明显。有效质量近似仅在某些情况下与紧束缚模型在电流-电压特性方面吻合得很好。一般来说，对于小直径导线，有效质量近似失效。
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet etching. In the method presented here gate-length control is limited by the resolution of the elec…
Weyl semimetals are characterized by their bulk Weyl points -- conical band touching points that carry a topological monopole charge -- and Fermi arc states that span between the Weyl points on the surface of the material. Recently, significant progress has been made towards understanding and measuring the physical properties of Weyl semimetals. Yet, potential applications remain relatively sparse. Here, we propose Weyl semimetal nanowires as field-effect transistors, dubbed WEYLFETs. Specifically, applying gradient gate voltage along the nanowire, an electrical field is generated that effecti…
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gated junctionless nanowire \emph{p}-type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with…
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we…
