Weyl semimetals are characterized by their bulk Weyl points -- conical band touching points that carry a topological monopole charge -- and Fermi arc states that span between the Weyl points on the surface of the material. Recently, significant progress has been made towards understanding and measuring the physical properties of Weyl semimetals. Yet, potential applications remain relatively sparse. Here, we propose Weyl semimetal nanowires as field-effect transistors, dubbed WEYLFETs. Specifically, applying gradient gate voltage along the nanowire, an electrical field is generated that effectively tilts the open surfaces, thus, varying the relative orientation between Fermi arcs on different surfaces. As a result, perfect negative refraction between adjacent surfaces can occur and longitudinal conductance along the wire is suppressed. The WEYLFET offers a high on/off ratio with low power consumption. Adverse effects due to dispersive Fermi arcs and surface disorder are studied.
We investigate the relaxation dynamics of photogenerated carriers in silicon nanowires consisting of a crystalline core and a surrounding amorphous shell, using femtosecond time-resolved differential reflectivity and transmission spectroscopy at photon energies of 3.15 eV and 1.57 eV. The complex behavior of the differential transmission and reflectivity transients is the mixed contributions from the crystalline core and the amorphous silicon on the nanowire surface and the substrate where competing effects of state filling and photoinduced absorption govern the carrier dynamics. Faster relaxa…
Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than th…
A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and ther…
In the present work, we have investigated the quantum transport in n Si junction less nanowire field effect transistors using 3 D, full band atomistic sp3d5s spin orbital coupled tight binding method. We have investigated the IDS VGS transfer characteristics, IDS VDS output characteristics, ON current, OFF current leakage, subthreshold swing and energy position resolved electron density spectrum Gn x, E in n Si junction less nanowire field effect transistors. We also study IDS VGS transfer characteristics with variation of High K gate materials. Quantum mechanical simulation is performed on th…
We report low-temperature electrical transport studies of molecule-scale silicon nanowires. Individual nanowires exhibit well-defined Coulomb blockade oscillations characteristic of charge addition to a single nanostructure with length scales up to at least 400 nm. Further studies demonstrate coherent charge transport through discrete single particle quantum levels extending the whole device, and show that the ground state spin configuration follows the Lieb-Mattis theorem. In addition, depletion of the nanowires suggests that phase coherent single-dot characteristics are accessible in a regim…
We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions are realized by low energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the nanowire resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and ON/O…
The ballistic performance of electron transport in nanowire transistors is examined using a 10 orbital sp3d5s* atomistic tight-binding model for the description of the electronic structure, and the top-of-the-barrier semiclassical ballistic model for calculation of the transport properties of the transistors. The dispersion is self consistently computed with a 2D Poisson solution for the electrostatic potential in the cross section of the wire. The effective mass of the nanowire changes significantly from the bulk value under strong quantization, and effects such as valley splitting strongly l…
Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the nanowire channel and the gate dielectric plays a crucial role in the FET performance, and it can be responsible for unwanted effects such as hysteresis of the I-V characteristics due to threshold voltage shift when the gate voltage is applied. Using gate-voltage bias stress measurements we show that a large hysteresis of up to 40V in Si NW FETs with SiO2 dielectric is mainly due to the holes traps at the nanowire/SiO2 interface. An approach for reducing this hyster…
In recent years, three-dimensional GaN-based transistors have been intensively studied for their dramatically improved output power, better gate controllability, and shorter channels for speedup and miniaturization. However, thermal analysis of such devices is often oversimplified using the conventional Fourier's law and bulk material properties in thermal simulations. In this aspect, accurate temperature predictions can be achieved by coupled phonon and electron Monte Carlo simulations that track the movement and scattering of individual phonons and electrons. However, the heavy computational…
We compare the electronic characteristics of nanowire field-effect transistors made using single pure wurtzite and pure zincblende InAs nanowires with nominally identical diameter. We compare the transfer characteristics and field-effect mobility versus temperature for these devices to better understand how differences in InAs phase govern the electronic properties of nanowire transistors.
Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ~1 nm wire diameter and ~3 nm gate length, and that the junctionless transistor may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration…
We analyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp3s*d5 tight-binding treatment of the electronic structure. Comparison of the measured performance of the device with the effects of series resistance removed to the simulated result assuming ballistic transport shows that the experimental device operates between 60 to 85% of the ballistic limit. For this ~15 nm diameter Ge nanowire, we also find that 14-18 modes are occupied at room temperature under ON-current conditions with ION/IOFF=100. To observe…
We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjace…
In this paper we present our progress towards the opto-electronic characterization of indium phosphide (InP) nanowire transistors at milli-Kelvin (mK) temperatures. First, we have investigated the electronic transport of the InP nanowires by current-voltage (I-V) spectroscopy as a function of temperature from 300 K down to 40 K. Second, we show the successful operation of a red light emitting diode (LED) at liquid-Helium (and base) temperature to be used for opto-electronic device characterization.
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gated junctionless nanowire \emph{p}-type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with…
In this letter, we explore the bandstructure effects on the performance of ballistic silicon nanowire transistors (SNWTs). The energy dispersion relations for silicon nanowires are evaluated with an sp3d5s* tight binding model. Based on the calculated dispersion relations, the ballistic currents for both n-type and p-type SNWTs are evaluated by using a semi-numerical ballistic model. For large diameter nanowires, we find that the ballistic p-SNWT delivers half the ON-current of a ballistic n-SNWT. For small diameters, however, the ON-current of the p-type SNWT approaches that of its n-type cou…
We propose the manipulation of Majorana edge states via hybridization and spin currents in a nanowire spin transistor. The spin transistor is based on a heterostructure nanowire comprising of semiconductors with large and small g-factors that form the topological and non-topological regions respectively. The hybridization of bound edge states results in spin currents and $4π$-periodic torques, as a function of the relative magnetic field angle -- an effect which is dual to the fractional Josephson effect. We establish relation between torques and spin-currents in the non-topological region whe…
This work investigates energy filtering in nanowires, where pass and stopbands are obtained by including superlattices in the wire. When a pair of such superlattices is placed in series, each being controlled by a gate, it can act as a transistor where the (mis-)alignment of its minibands turns the device on (off). It is shown that, in the ballistic current-regime, the transition between the on and off state occurs in a narrow gate-bias range, giving rise to sub-60 mV per decade switching behavior.
We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising …
We report the operation of a field-effect transistor based on a single InAs nanowire gated by an ionic liquid. Liquid gating yields very efficient carrier modulation with a transconductance value thirty time larger than standard back gating with the SiO2 /Si++ substrate. Thanks to this wide modulation we show the controlled evolution from semiconductor to metallic-like behavior in the nanowire. This work provides the first systematic study of ionic-liquid gating in electronic devices based on individual III-V semiconductor nanowires: we argue this architecture opens the way to a wide range of …
In this letter, we report a three-dimensional (3D) quantum mechanical simulation to investigate the effects of surface roughness scattering (SRS) on the device characteristics of Si nanowire transistors (SNWTs). We treat the microscopic structure of the Si/SiO2 interface roughness directly by using a 3D finite element technique. The results show that 1) SRS reduces the electron density of states in the channel, which increases the SNWT threshold voltage, and 2) the SRS in SNWTs becomes more effective when more propagating modes are occupied, which implies that SRS is more important in planar m…
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the…
In this article, we present a configurable field-effect transistor (FET), where not only polarity (n- and p-type), but the conduction mechanism of a FET can also be configured dynamically. As a result, we can have both types of devices, high-performance MOSFET and low-power TFET, for computational and power efficient system on chip (SoC) products. The calibrated 3D-TCAD simulation results validate characteristics and functionalities of the configurable FET, and showed good consistency with the static conventional MOSFET (or TFET).
We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO$_{4}$ polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale de…
Solution processed field-effect transistors based on single crystalline silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The semiconducting layer was deposited from a nanowire ink formulation at room temperature. The devices with 230nm thick SiO2 gate insulating layers show excellent output current-voltage characteristics with early saturation voltages under 2 volts, constant saturation current and exceptionally low dependence of saturation voltage with the gate field. Operational principles of these devices are markedly different from traditional ohmic-contact field-e…
In this study, InSb nanowires have been formed by electrodeposition and integrated into NW-FETs. NWs were formed in porous anodic alumina (PAA) templates, with the PAA pore diameter of approximately 100 nm defining the NW diameter. Following annealing at 125C and 420C respectively, the nanowires exhibited the zinc blende crystalline structure of InSb, as confirmed from x-ray diffraction and high resolution transmission electron microscopy. The annealed nanowires were used to fabricate nanowire field effect transistors (NW-FET) each containing a single NW with 500 nm channel length and gating t…
The intermediate transport regime in nanoscale transistors between the fully ballistic case and the quasi equilibrium case described by the drift-diffusion model is still an open modeling issue. Analytical approaches to the problem have been proposed, based on the introduction of a backscattering coefficient, or numerical approaches consisting in the MonteCarlo solution of the Boltzmann transport equation or in the introduction of dissipation in quantum transport descriptions. In this paper we propose a very simple analytical model to seamlessly cover the whole range of transport regimes in ge…
We present a theoretical framework for the calculation of charge transport through nanowire-based Schottky-barrier field-effect transistors that is conceptually simple but still captures the relevant physical mechanisms of the transport process. Our approach combines two approaches on different length scales: (1) the finite elements method is used to model realistic device geometries and to calculate the electrostatic potential across the Schottky-barrier by solving the Poisson equation, and (2) the Landauer approach combined with the method of non-equilibrium Green's functions is employed to …
Millivolt range thermovoltage is demonstrated in single InAs-nanowire based field effect transistors. Thanks to a buried heating scheme, we drive both a large thermal bias DT>10K and a strong field-effect modulation of electric conductance on the nanostructures. This allows the precise mapping of the evolution of the Seebeck coefficient S as a function of the gate-controlled conductivity between room temperature and 100K$. Based on these experimental data a novel estimate of the electron mobility is given. This value is compared with the result of standard field-effect based mobility estimates…
Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive geometries. In this paper, we explore a similar architecture for aggressively scaled devices with the channel consisting of doped carbon nanotubes (CNTs). Gate all around (GAA) field effect transistor (FET) structures are investigated for n- and p-type doping. Current-voltage characteristics and sub-threshold characteristics for a CNTbased junctionless FET i…
We report on the observation of Coulomb oscillations from localized quantum dots superimposed on the normal hopping current in ZnO nanowire transistors. The Coulomb oscillations can be resolved up to 20 K. Positive anisotropic magnetoresistance has been observed due to the Lorentz force on the carrier motion. Magnetic field-induced tunneling barrier transparency results in an increase of oscillation amplitude with increasing magnetic field. The energy shift as a function of magnetic field indicates electron wavefunction modification in the quantum dots.
In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from 3D to 4D structure has been developed and summarized. The successful fabrication of InGaAs lateral and vertical NW arrays has led to 4x increase in MOSFET drive current. The top-down technology developed in this paper has opened a viable pathway towards future low-power logic and RF transistors with high-density III-V NWs.
Atomistic quantum transport simulation of realistically large devices is computationally very demanding. The widely used mode space (MS) approach can significantly reduce the numerical cost but good MS basis is usually very hard to obtain for atomistic full-band models. In this work, a robust and parallel algorithm is developed to optimize the MS basis for atomistic nanowires. This enables tight binding non-equilibrium Green's function (NEGF) simulation of nanowire MOSFET with realistic cross section of $\rm 10nm\times10nm$ using a small computer cluster. This approach is applied to compare th…
We investigate the mechanisms responsible for the low-frequency noise in liquid-gated nano-scale silicon nanowire field-effect transistors (SiNW-FETs) and show that the charge-noise level is lower than elementary charge. Our measurements also show that ionic strength of the surrounding electrolyte has a minimal effect on the overall noise. Dielectric polarization noise seems to be at the origin of the 1/f noise in our devices. The estimated spectral density of charge noise Sq = 1.6x10-2 e/sqr(Hz) at 10 Hz opens the door to metrological studies with these SiNW-FETs for the electrical detection …
In this work, we present a quantum mechanical approach for the simulation of Si/SiO2 interface roughness scattering in silicon nanowire transistors (SNWTs). The simulation domain is discretized with a three-dimensional (3D) finite element mesh, and the microscopic structure of the Si/SiO2 interface roughness is directly implemented. The 3D Schrodinger equation with open boundary conditions is solved by the non-equilibrium Green's function method together with the coupled mode space approach. The 3D electrostatics in the device is rigorously treated by solving a 3D Poisson equation with the fin…
This paper examines the validity of the widely-used parabolic effective-mass approximation for computing the current-voltage (I-V) characteristics of silicon nanowire transistors (SNWTs). The energy dispersion relations for unrelaxed Si nanowires are first computed by using an sp3d5s* tight-binding model. A semi-numerical ballistic FET model is then adopted to evaluate the I-V characteristics of the (n-type) SNWTs based on both a tight-binding dispersion relation and parabolic energy bands. In comparison with the tight-binding approach, the parabolic effective-mass model with bulk effective-ma…
The effects of an atomistic interface roughness in n-type silicon nanowire transistors (SiNWT) on the radio frequency performance are analyzed. Interface roughness scattering (IRS) is statistically investigated through a three dimensional full-band quantum transport simulation based on the sp3d5s?* tight-binding model. As the diameter of the SiNWT is scaled down below 3 nm, IRS causes a significant reduction of the cut-off frequency. The fluctuations of the conduction band edge due to the rough surface lead to a reflection of electrons through mode-mismatch. This effect reduces the velocity of…
We report on fabrication of single-electron transistors using InAs nanowires with epitaxial aluminium with fixed tunnel barriers made of aluminium oxide. The devices exhibit a hard superconducting gap induced by the proximized aluminium cover shell and they behave as metallic single-electron transistors. In contrast to the typical few channel contacts in semiconducting devices, our approach forms opaque multichannel contacts to a semiconducting wire and thus provides a complementary way to study them. In addition, we confirm that unwanted extra quantum dots can appear at the surface of the nan…
We demonstrate the proof of principle for a ternary adder using silicon metal-on-insulator single electron transistors (SET). Gate dependent rectifying behavior of a single electron transistor results in a robust three-valued output as a function of the potential of the SET island. Mapping logical, ternary inputs to the three gates controlling the potential of the SET island allows us to perform complex, inherently ternary operations, on a single transistor.
Effective electron mobilities are obtained by transport measurements on InAs nanowire field-effect transistors at temperatures ranging from 10-200 K. The mobility increases with temperature below ~ 30 - 50 K, and then decreases with temperature above 50 K, consistent with other reports. The magnitude and temperature dependence of the observed mobility can be explained by Coulomb scattering from ionized surface states at typical densities. The behaviour above 50 K is ascribed to the thermally activated increase in the number of scatterers, although nanoscale confinement also plays a role as hig…
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet etching. In the method presented here gate-length control is limited by the resolution of the elec…
Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been identified as the main source of noise at low frequency. It often originates from an ensemble of a huge number of charges trapping and detrapping. However, a deviation from the well-known model of 1/f noise is observed for nanoscale MOSFETs and a new model is required. Here, we report the observation of one-by-one trap activation controlled by the gate voltage in a nanowire MOSFET and we propose a new low-frequency-noise theory for nanoscale FETs. We demonstrate that the Coulomb repulsion between elec…
We compare the characteristics of phase-pure MOCVD grown ZB and WZ InAs nanowire transistors in several atmospheres: air, dry pure N$_2$ and O$_2$, and N$_2$ bubbled through liquid H$_2$O and alcohols to identify whether phase-related structural/surface differences affect their response. Both WZ and ZB give poor gate characteristics in dry state. Adsorption of polar species reduces off-current by 2-3 orders of magnitude, increases on-off ratio and significantly reduces sub-threshold slope. The key difference is the greater sensitivity of WZ to low adsorbate level. We attribute this to facet st…
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we…
At a superconductor (S)-normal metal (N) junction pairing correlations can "leak-out" into the N region. This proximity effect [1, 2] modifies the system transport properties and can lead to supercurrent flow in SNS junctions [3]. Recent experimental works showed the potential of semiconductor nanowires (NWs) as building blocks for nanometre-scale devices [4-7], also in combination with superconducting elements [8-12]. Here, we demonstrate an InAs NW Josephson transistor where supercurrent is controlled by hot-quasiparticle injection from normal-metal electrodes. Operational principle is based…
The theoretical description has been proposed for the operation of the spin transistor in the gate-controlled InAs nanowire. The calculated current-voltage characteristics show that the current flowing from the source (spin injector) to the drain (spin detector) oscillates as a function of the gate voltage, which results from the precession of the electron spin caused by the Rashba spin-orbit interaction in the vicinity of the gate. We have studied two operation modes of the spin transistor: (A) the ideal operation mode with the full spin polarization of electrons in the contacts, the zero tem…
The Cooper-pair transistor (CPT), a small superconducting island enclosed between two Josephson weak links, is the atomic building block of various superconducting quantum circuits. Utilizing gate-tunable semiconductor channels as weak links, the energy scale associated with the Josephson tunneling can be changed with respect to the charging energy of the island, tuning the extent of its charge fluctuations. Here, we directly demonstrate this control by mapping the energy level structure of a CPT made of an indium arsenide nanowire (NW) with a superconducting aluminum shell. We extract the dev…
An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contact…
We investigate the low temperature transport in 8 nm diameter Si junctionless nanowire field effect transistors fabricated by top down techniques with a wrap-around gate and two different activated doping densities. First we extract the intrinsic gate capacitance of the device geometry from a device that shows Coulomb blockade at 13 mK with over 500 Coulomb peaks across a gate voltage range of 6 V indicating the formation of a single island in the entire nanowire channel. In two other devices, doped Si:P $4\times10^{19}\,\text{cm}^{-3}$ and $2\times10^{20}\,\text{cm}^{-3}$, we observe quantum …
Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ra…
A 20 band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding (TB) model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to theoretically examine the bandstructure carrier velocity and ballistic current in silicon nanowire (NW) transistors. Infinitely long, uniform, cylindrical and rectangular NWs, of cross sectional diameters/sides ranging from 3nm to 12nm are considered. For a comprehensive analysis, n-type and p-type metal-oxide-semiconductor (NMOS and PMOS) NWs in [100], [110] and [111] transport orientations are examined. In general, physical…
Understanding of the electrical contact properties of semiconductor nanowire (NW) field effect transistors (FETs) plays a crucial role in employing semiconducting NWs as building blocks for future nanoelectronic devices and in the study of fundamental physics problems. Here, we report on a study of the contact properties of Ti/Au, a widely used contact metal combination, to individual InSb NWs via both two-probe and four-probe transport measurements. We show that a Schottky barrier of height $Φ_{\rm{SB}}\sim20\ \rm{meV}$ is present at the metal-InSb NW interfaces and its effective height is ga…
Parity control of superconducting islands hosting Majorana zero modes (MZMs) is required to operate topological qubits made from proximitized semiconductor nanowires. We, therefore, study parity effects in hybrid InAs-Al single-Cooper-pair transistors (SCPTs) as a first step. In particular, we investigate the gate-charge supercurrent modulation and observe a consistent 2$e$-periodic pattern indicating a general lack of low-energy subgap states in these nanowires at zero magnetic field. In a parallel magnetic field, an even-odd pattern develops with a gate-charge spacing that oscillates as a fu…
We study a Cooper-pair transistor realized by two Josephson weak links that enclose a superconducting island in an InSb-Al hybrid nanowire. When the nanowire is subject to a magnetic field, isolated subgap levels arise in the superconducting island and, due to the Coulomb blockade,mediate a supercurrent by coherent co-tunneling of Cooper pairs. We show that the supercurrent resulting from such co-tunneling events exhibits, for low to moderate magnetic fields, a phase offset that discriminates even and odd charge ground states on the superconducting island. Notably,this phase offset persists wh…
In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design…
This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the first-order perturbation theory for calculating eigenstates and corresponding wave functions obtained by the Schrodinger equation in the cylindrical coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step towar…
