We have fabricated n-layer graphene field effect transistors on epitaxial ferroelectric Pb(Zr_0.2Ti_0.8)O_3 (PZT) thin films. At low gate voltages, PZT behaves as a high-k dielectric with k up to 100. An unusual resistance hysteresis occurs in gate sweeps at high voltages, with its direction opposite to that expected from the polarization switching of PZT. The relaxation of the metastable state is thermally activated, with an activation barrier of 50-110 meV and a time constant of 6 hours at 300 K. We attribute its origin to the slow dissociation/recombination dynamics of water molecules adsorbed at the graphene-PZT interface. This robust hysteresis can potentially be used to construct graphene-ferroelectric hybrid memory devices.
Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the nanowire channel and the gate dielectric plays a crucial role in the FET performance, and it can be responsible for unwanted effects such as hysteresis of the I-V characteristics due to threshold voltage shift when the gate voltage is applied. Using gate-voltage bias stress measurements we show that a large hysteresis of up to 40V in Si NW FETs with SiO2 dielectric is mainly due to the holes traps at the nanowire/SiO2 interface. An approach for reducing this hyster…
The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of…
A transition in source-drain current vs back gate voltage ID - VBG characteristics from extrinsic polar molecule dominant hysteresis to anti-hysteresis induced by an oxygen deficient surface layer that is intrinsic to the ferroelectric thin films has been observed on graphene field-effect transistors on Pb0.92La0.08Zr0.52Ti0.48O3 gates GFET/PLZT-Gate during a vacuum annealing process developed to systematically remove the polar molecules adsorbed on the GFET channel surface. This allows detangle of the extrinsic and intrinsic hysteresis on GFET/PLZT-gate devices and detection of the dynamic sw…
We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, beside…
We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two…
Graphene field effect transistors commonly comprise graphene flakes lying on SiO2 surfaces. The gate-voltage dependent conductance shows hysteresis depending on the gate sweeping rate/range. It is shown here that the transistors exhibit two different kinds of hysteresis in their electrical characteristics. Charge transfer causes a positive shift in the gate voltage of the minimum conductance, while capacitive gating can cause the negative shift of conductance with respect to gate voltage. The positive hysteretic phenomena decay with an increase of the number of layers in graphene flakes. Self-…
Understanding the origin of hysteresis in the channel resistance from top gated graphene transistors is important for transistor applications. Capacitance - voltage measurements across the gate oxide on top gated bilayer graphene show hysteresis with a charging and discharging time constant of ~100 μs. However, the measured capacitance across the graphene channel does not show any hysteresis, but shows an abrupt jump at a high channel voltage due to the emergence of an order, indicating that the origin of hysteresis between gate and source is due to charge traps present in the gate oxide and g…
The possible existence of short-channel effects in oxide field-effect transistors is investigated by exploring field-effect transistors with various gate lengths fabricated from LaAlO$_3$-SrTiO$_3$ heterostructures. The studies reveal the existence of channel-length modulation and drain-induced barrier lowering for gate lengths below 1 μm, with a characteristic behavior comparable to semiconducting devices. With the fabrication of field-effect transistors with gate lengths as small as 60 nm the results demonstrate the possibility to fabricate by electron-beam lithography functional devices bas…
Hysteresis and commonly observed p-doping of graphene based field effect transistors (FET) was already discussed in reports over last few years. However, the interpretation of experimental works differs; and the mechanism behind the appearance of the hysteresis and the role of charge transfer between graphene and its environment are not clarified yet. We analyze the relation between electrochemical and electronic properties of graphene FET in moist environment extracted from the standard back gate dependence of the graphene resistance. We argue that graphene based FET on a regular SiO2 substra…
We have fabricated quantum dot single electron transistors, based on AlGaAs/GaAs heterojunctions without modulation doping, which exhibit clear and stable Coulomb blockade oscillations. The temperature dependence of the Coulomb blockade peak lineshape is well described by standard Coulomb blockade theory in the quantum regime. Bias spectroscopy measurements have allowed us to directly extract the charging energy, and showed clear evidence of excited state transport, confirming that individual quantum states in the dot can be resolved.
We report room-temperature Coulomb blockade in a single layer graphene three-terminal single-electron transistor (SET) fabricated using feedback-controlled electroburning. The small separation between the side gate electrode and the graphene quantum dot results in a gate coupling up to 3 times larger compared to the value found for the back gate electrode. This allows for an effective tuning between the conductive and Coulomb blocked state using a small side gate voltage of about 1V. The technique can potentially be used in the future to fabricate all-graphene based room temperature single-ele…
Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designin…
The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS$_2$ transistors back-gated by single-layer polycrystalline PbZr$_{0.35}$Ti$_{0.65}$O$_3$. The devices exhibit current on/off ratios up to 8$\times$10$^6$ within an ultra-low gate voltage window of $V_g$ = $\pm$0.5 V and subthreshold swing (SS) as low as 9.7 mV …
A few-layer palladium diselenide (PdSe2) field effect transistor is studied under external stimuli such as electrical and optical fields, electron irradiation and gas pressure. We observe ambipolar conduction and hysteresis in the transfer curves of the PdSe2 material unprotected and as-exfoliated. We tune the ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments. The prevailing p-type transport observed at room pressure is reversibly turned into dominant n-type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The press…
In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance,…
A new method to fabricate non-superconducting mesoscopic tunnel junctions by oxidation of Ti is presented. The fabrication process uses conventional electron beam lithography and shadow deposition through an organic resist mask. Superconductivity in Ti is suppressed by performing the deposition under a suitable background pressure. We demonstrate the method by making a single electron transistor which operated at $T < 0.4$ K and had a moderate charge noise of $2.5 \times 10^{-3}$ e/$\sqrt{\mathrm{Hz}}$ at 10 Hz. Based on nonlinearities in the current-voltage characteristics at higher voltages,…
The carrier mobility μof few-layer graphene (FLG) field-effect transistors increases ten-fold when the SiO_2 substrate is replaced by single-crystal epitaxial Pb(Zr_0.2Ti_0.8)O_3 (PZT). In the electron-only regime of the FLG, μreaches 7x10^4 cm^2/Vs at 300K for n = 2.4x10^12/cm^2, 70% of the intrinsic limit set by longitudinal acoustic (LA) phonons; it increases to 1.4x10^5 cm^2/Vs at low temperature. The temperature-dependent resistivity ρ(T) reveals a clear signature of LA phonon scattering, yielding a deformation potential D = 7.8+/-0.5 eV.
Supplementary Information to arXiv:0810.4466: 1. Characterizations of Pb(Zr_0.2Ti_0.8)O_3 (PZT) films. 2. Substrate preparation before the exfoliation of graphene. 3. The band structure of FLG. 4. Dielectric constant measurements of PZT. 5. rho(V_g) and R_H(V_g) fitting inside the band overlap regime. 6. The deformation potential of longitudinal acoustic (LA) phonons in graphene. 7. Resistivity and Hall measurements of a SiO_2-gated FLG.
Steep-slope $β$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate voltage sweeps with a minimum value of 34.3 mV/dec at reverse gate voltage sweep and 53.1 mV/dec at forward gate voltage sweep at $V_{DS}$=0.5 V. Enhancement-mode operation with threshold voltage ~0.4 V is achieved by tuning the thickness of $β$-Ga$_2$O$_3$ membrane. Low hysteresis of less than 0.1 V is obtain…
Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally-decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal arrangement of carbon atoms with the correct lattice vectors, observed by high-resolution scanning tunneling microscopy, confirms the formation of multiple graphene layers on top of the SiC substrates. The observation of n-type and p-type transition further verifies Dirac Fermions unique transport properties in graphene layers. The measured electron and hole …
A single-electron transistor has been realized in a Ga[Al]As heterostructure by oxidizing lines in the GaAs cap layer with an atomic force microscope. The oxide lines define the boundaries of the quantum dot, the in-plane gate electrodes, and the contacts of the dot to source and drain. Both the number of electrons in the dot as well as its coupling to the leads can be tuned with an additional, homogeneous top gate electrode. Pronounced Coulomb blockade oscillations are observed as a function of voltages applied to different gates. We find that, for positive top-gate voltages, the lithographic…
We have fabricated transistor structures using fluorinated single-layer graphene flakes and studied their electronic properties at different temperatures. Compared with pristine graphene, fluorinated graphene has very large and strongly temperature dependent resistance in the electro-neutrality region. We show that fluorination creates a mobility gap in graphene's spectrum where electron transport takes place via localised electron states.
We present the results of the experimental investigation of the low - frequency noise in bilayer graphene transistors. The back - gated devices were fabricated using the electron beam lithography and evaporation. The charge neutrality point for the fabricated transistors was around 10 V. The noise spectra at frequencies above 10 - 100 Hz were of the 1/f - type with the spectral density on the order of 10E-23 - 10E-22 A2/Hz at the frequency of 1 kHz. The deviation from the 1/f spectrum at the frequencies below 10 -100 Hz indicates that the noise is of the carrier - number fluctuation origin due…
We have fabricated suspended few layer (1-3 layers) graphene nanoribbon field effect transistors from unzipped multiwall carbon nanotubes. Electrical transport measurements show that current-annealing effectively removes the impurities on the suspended graphene nanoribbons, uncovering the intrinsic ambipolar transfer characteristic of graphene. Further increasing the annealing current creates a narrow constriction in the ribbon, leading to the formation of a large band-gap and subsequent high on/off ratio (which can exceed 104). Such fabricated devices are thermally and mechanically stable: re…
Junctionless oxide-based neuron thin-film transistors with in-plane-gate structure are fabricated at room temperature with a laser scribing process. The neuron transistors are composed of a bottom ITO floating gate and multiples of two in-plane control gates. The control gates, coupling with the floating gate, control the "on" and "off" of the transistor. Effective field-effect modulation of the drain current has been realized. AND logic is demonstrated on a dual in-plane gate neuron transistor. The developed laser scribing technology is highly desirable in terms of the fabrication of high per…
We have fabricated carbon nanotube (CN) field-effect transistors with multiple, individually addressable gate segments. The devices exhibit markedly different transistor characteristics when switched using gate segments controlling the device interior versus those near the source and drain. We ascribe this difference to a change from Schottky barrier modulation at the contacts to bulk switching. We also find that the current through the bulk portion is independent of gate length for any gate voltage, offering direct evidence for ballistic transport in semiconducting CNs over at least a few hun…
In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design…
We have fabricated and measured ballistic graphene transistors with two oblique gates that can be independently biased. The gate lengths are about 38 nm and are separated by a distance of 30 nm, the tilting angle being of 45o with respect to source and drain electrodes distanced at 190 nm. Electric measurements reveal specific properties of ballistic carrier transport, i.e. nonlinear drain voltage-drain current dependence, showing a saturation region, and negative differential resistance at certain bias voltages, which cannot be explained without physical mechanisms related to ballistic transp…
Graphene nanoribbon (GNR) field-effect transistors (FETs) with widths down to 12 nm have been fabricated by electron beam lithography using a wafer-scale chemical vapor deposition (CVD) process to form the graphene. The GNR FETs show drain-current modulation of approximately 10 at 300 K, increasing to nearly 106 at 4 K. The strong temperature dependence of the minimum current indicates the opening of a bandgap for CVD-grown GNR-FETs. The extracted bandgap is estimated to be around 0.1 eV by differential conductance methods. This work highlights the development of CVD-grown large-area graphene …
We report about the fabrication and analysis of the properties of Cr/CrO_x/Cr tunnel junctions and SET transistors, prepared by different variants of direct-writing multilayer technique. In all cases, the CrO_x tunnel barriers were formed in air under ambient conditions. From the experiments on single junctions, values for the effective barrier height and thickness were derived. For the Cr/CrO_x/Cr SET transistors we achieved minimal junction areas of 17 x 60 nm^2 using a scanning transmission electron microscope for the e-beam exposure on Si_3N_4 membrane substrate. We discuss the electrical …
A novel graphene transistor architecture is reported. The transistor has a U-shape geometry and was fabricated using a gallium focused ion beam (FIB). The channel conductance was tuned with a back gate. The Ion/Ioff ratio exceeded 10^5.
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying…
Physical phenomena underlying operation of ferroelectric field-effect transistors (FeFETs) is treated within a unified simulation framework. The framework incorporates the Landau mean-field treatment of free energy of a ferroelectric and the polarization dynamics according to Landau-Khalatnikov (LK) equation. These equations are self-consistently solved with the one-dimensional metal-oxide-semiconductor (MOS) structure electrostatics and the drift-diffusion solution for the current in the semiconductor channel. Numerical simulations demonstrate, depending on the ferroelectric (FE) thickness, b…
A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and ther…
We have fabricated a grating-gate InGaAs/GaAs field-effect transistor structure with narrow slits between the grating gate fingers. The resonant photoconductive response of this structure has been measured in the sub-terahertz frequency range. The frequencies of the photoresponse peaks correspond to the excitation of the plasmon resonances in the structure channel. The obtained responsivity exceeds the responsivity reported previously for similar plasmonic terahertz detectors by two orders of magnitude due to enhanced coupling between incoming terahertz radiation and plasmon oscillations in th…
We propose a modified spin-field-effect transistor fabricated in a two dimensional electron gas (2DEG) formed at the surface of multiferroic oxides with a transverse helical magnetic order. The topology of the oxide local magnetic moments induces a resonant momentum-dependent effective spin-orbit interaction acting on 2DEG. We show that spin polarization dephasing is strongly suppressed which is crucial for functionality. The carrier spin precession phase depend linearly on the magnetic spiral helicity. The latter is electrically controllable by virtue of the magento-electric effect. We also s…
We present the first study of the intrinsic electrical properties of WS$_2$ transistors fabricated with two different dielectric environments WS$_2$ on SiO$_2$ and WS$_2$ on h-BN/SiO$_2$, respectively. A comparative analysis of the electrical characteristics of multiple transistors fabricated from natural and synthetic WS$_2$ with various thicknesses from single- up to four-layers and over a wide temperature range from 300K down to 4.2 K shows that disorder intrinsic to WS$_2$ is currently the limiting factor of the electrical properties of this material. These results shed light on the role p…
Liquid-based applications of biomolecule-decorated field-effect transistors (FETs) range from biosensors to in vivo implants. A critical scientific challenge is to develop a quantitative understanding of the gating effect of charged biomolecules in ionic solution and how this influences the readout of the FETs. To address this issue, we fabricated protein-decorated graphene FETs and measured their electrical properties, specifically the shift in Dirac voltage, in solutions of varying ionic strength. We found excellent quantitative agreement with a model that accounts for both the graphene pola…
In this work, an evaluation of the contact quality of black phosphorus (BP) field-effect transistors (FETs) from different technologies previously reported is performed by means of an efficient and reliable contact resistance extraction methodology based on individual device practical characteristics. A good agreement is achieved between the extracted values with the Y-function method used here and reference values obtained with other methods considering internal values as well as with more expensive methods involving fabricated test structures. The method enables a direct evaluation of differ…
The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High…
We have fabricated aluminum single-electron transistors in which the island is not in contact with the substrate. This new type of device, which can be called suspended single-electron transistor (SUSET), displayed well-defined I-V and dI/dV-V features typical for high-quality standard SET's.
Single electron transistors (SETs) made from single wall carbon nanotubes (SWCNTs) are promising for quantum electronic devices operating with ultra-low power consumption and allow fundamental studies of electron transport. We report on SETs made by registered in-plane growth utilizing tailored nanoscale catalyst patterns and chemical vapor deposition. Metallic SWCNTs have been removed by an electrical burn-in technique and the common gate hysteresis was removed using PMMA and baking, leading to field effect transistors with large on/off ratios up to 10^5. Further segmentation into 200 nm shor…
Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.
We report on "graphene-like" mechanical exfoliation of thin films of titanium ditelluride and investigation of their electronic properties. The exfoliated crystalline TiTe2 films were used as the channel layers in the back-gated field-effect transistors fabricated with Ti/Al/Au metal contacts on SiO2/Si substrates. The room-temperature current-voltage characteristics revealed strongly non-linear behavior with signatures of the source-drain threshold voltage similar to those observed in the charge-density-wave devices. The drain-current showed an unusual non-monotonic dependence on the gate bia…
We report the realization of top-gated graphene nanoribbon field effect transistors (GNRFETs) of ~10 nm width on large-area epitaxial graphene exhibiting the opening of a band gap of ~0.14 eV. Contrary to prior observations of disordered transport and severe edge-roughness effects of GNRs, the experimental results presented here clearly show that the transport mechanism in carefully fabricated GNRFETs is conventional band-transport at room temperature, and inter-band tunneling at low temperature. The entire space of temperature, size, and geometry dependent transport properties and electrostat…
High-performance single-wall carbon nanotube field-effect transistors (SWNT-FETs) are fabricated using directed assembly and mass-produced carbon nanotubes (CNTs). These FETs exhibit operating characteristics comparable to state-of-the-art devices, and the process provides a route to large-scale functional CNT circuit assembly that circumvents problems inherent in processes relying on chemical vapor deposition (CVD). Furthermore, the integration of hydrophobic self-assembled monolayers (SAMs) in the device structure eliminates the primary source of gating hysteresis in SWNT-FETs, which leads t…
We demonstrate a graphene-MoS2 architecture integrating multiple field-effect transistors and we independently probe and correlate the conducting properties of van der Waals coupled graphene-MoS2 contacts with the ones of the MoS2 channels. Devices are fabricated starting from high-quality single-crystal monolayers grown by chemical vapor deposition and characterized by scanning Raman and photoluminescence spectroscopies. Transconductance curves of MoS2 are compared with the current-voltage characteristics of graphene contact stripes, revealing a significant suppression of transport on the n-s…
For the first time, n-type few-layer MoS2 field-effect transistors with graphene/Ti as the hetero-contacts have been fabricated, showing more than 160 mA/mm drain current at 1 μm gate length with an on-off current ratio of 107. The enhanced electrical characteristic is confirmed in a nearly 2.1 times improvement in on-resistance and a 3.3 times improvement in contact resistance with hetero-contacts compared to the MoS2 FETs without graphene contact layer. Temperature dependent study on MoS2/graphene hetero-contacts has been also performed, still unveiling its Schottky contact nature. Transfer …
Ferromagnetic single electron transistors with Al islands and orthogonal ferromagnetic leads (Co) are fabricated using ebeam lithography followed by shadow evaporation techniques. I-V characteristics exhibit typical single electron tunneling effects. Transport measurements performed in external magnetic field show that, when the two ferromagnetic leads are in antiparallel configuration, spin imbalance leads to a suppression of superconductivity.
We demonstrated selective gas sensing with MoS2 thin-film transistors using the change in the channel conductance, characteristic transient time and low-frequency current fluctuations as the sensing parameters. The back-gated MoS2 thin-film field-effect transistors were fabricated on Si/SiO2 substrates and intentionally aged for a month to verify reliability and achieve better current stability. The same devices with the channel covered by 10 nm of Al2O3 were used as reference samples. The exposure to ethanol, acetonitrile, toluene, chloroform, and methanol vapors results in drastic changes in…
Spin transistors (whose on-off operation is achieved by electric-field-controlled spin orientation 1), if realized, can revolutionize modern electronics through the implementation of a faster and a more energy-efficient performance as well as non-volatile data storage 2, 3. The original proposal by Datta and Das 1 that relies on electric-field-controlled spin precession in a semiconductor channel faces significant challenges including inefficient spin injection, spin relaxation and spread of the spin precession angle 4, 5. Recent demonstration of electric-field switching of magnetic order 6-8 …
We report on room temperature THz detection by means of antenna-coupled field effect transistors fabricated by using epitaxial graphene grown on silicon carbide substrate. Two independent detection mechanisms are found: plasma wave assisted-detection and thermoelectric effect, which is ascribed to the presence of junctions along the FET channel. The superposition of the calculated functional dependence of both the plasmonic and thermoelectric photovoltages on the gate bias qualitatively well reproduces the measured photovoltages. Additionally, the sign reversal of the measured photovoltage dem…
