The scattering of conduction electrons off neutral donors depends sensitively on the relative orientation of their spin states. We present a theory of spin-dependent scattering in the two dimensional electron gas (2DEG) of field effect transistors. Our theory shows that the scattering mechanism is dominated by virtual transitions to negatively ionized donor levels. This effect translates into a source-drain current that always gets reduced when donor spins are at resonance with a strong microwave field. We propose a model for donor impurities interacting with conduction electrons in a silicon transistor, and compare our explicit numerical calculations to electrically detected magnetic resonance (EDMR) experiments. Remarkably, we show that EDMR is optimal for donors placed into a sweet spot located at a narrow depth window quite far from the 2DEG interface. This allows significant optimization of spin signal intensity for the minimal number of donors placed into the sweet spot, enabling the development of single spin readout devices. Our theory reveals an interesting dependence on conduction electron spin polarization p_c. As p_c increases upon spin injection, the EDMR amplitude first increases as p_{c}^{2}, and then saturates when a polarization threshold p_T is reached. These results show that it is possible to use EDMR as an in-situ probe of carrier spin polarization in silicon and other materials with weak spin-orbit coupling.
A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and ther…
Graphene/silicon heterostructures have attracted tremendous interest as a new platform for diverse electronic and photonic devices such as barristors, solar cells, optical modulators, and chemical sensors. The studies to date largely focus on junctions between graphene and lightly-doped silicon, where a Schottky barrier is believed to dominate the carrier transport process. Here we report a systematic investigation of carrier transport across the heterojunctions formed between graphene and highly-doped silicon. By varying the silicon doping level and the measurement temperature, we show that t…
We report electrically detected magnetic resonance of phosphorus donors in a silicon field-effect transistor. An on-chip transmission line is used to generate the oscillating magnetic field allowing broadband operation. At milli-kelvin temperatures, continuous wave spectra were obtained up to 40 GHz, using both magnetic field and microwave frequency modulation. The spectra reveal the hyperfine-split electron spin resonances characteristic for Si:P and a central feature which displays the fingerprint of spin-spin scattering in the two-dimensional electron gas.
We report low-temperature electrical transport studies of molecule-scale silicon nanowires. Individual nanowires exhibit well-defined Coulomb blockade oscillations characteristic of charge addition to a single nanostructure with length scales up to at least 400 nm. Further studies demonstrate coherent charge transport through discrete single particle quantum levels extending the whole device, and show that the ground state spin configuration follows the Lieb-Mattis theorem. In addition, depletion of the nanowires suggests that phase coherent single-dot characteristics are accessible in a regim…
We present a realisation of high bandwidth instrumentation at cryogenic temperatures and for dilution refrigerator operation that possesses advantages over methods using radio-frequency single electron transistor or transimpedance amplifiers. The ability for the low temperature electronics to carry out faster measurements than with room temperature electronics is investigated by the use of a phosphorous-doped single-electron transistor. A single-shot technique is successfully implemented and used to observe the real time decay of a quantum state. A discussion on various measurement strategies …
We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising …
We integrate ambipolar quantum dots in silicon fin field-effect transistors using exclusively standard complementary metal-oxide-semiconductor fabrication techniques. We realize ambipolarity by replacing conventional highly-doped source and drain electrodes by a metallic nickel silicide with Fermi level close to the silicon mid-gap position. Such devices operate in a dual mode, either as classical field-effect or single-electron transistor. We implement a classical logic NOT gate at low temperature by tuning two interconnected transistors into opposite polarities. In the quantum regime, we dem…
We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call Graphene Base Transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 50.000.
By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost in…
In this manuscript, we present a field effect transistor with a channel consisting of a two-dimensional electron gas located at the interface between an ultrathin metallic film of Ni and a p-type Si(111) substrate. We have demonstrated that the two-dimensional electron gas channel is modulated by the gate voltage. The dependence of the drain current on the drain voltage has no saturation region, similar to a field effect transistor based on graphene. However, the transport in this transistor is not ambipolar, as in graphene, but unipolar.
In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect- Transistor (MOSFET) in which the front gate consists of two materials with different work functions.
Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive geometries. In this paper, we explore a similar architecture for aggressively scaled devices with the channel consisting of doped carbon nanotubes (CNTs). Gate all around (GAA) field effect transistor (FET) structures are investigated for n- and p-type doping. Current-voltage characteristics and sub-threshold characteristics for a CNTbased junctionless FET i…
Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the nanowire channel and the gate dielectric plays a crucial role in the FET performance, and it can be responsible for unwanted effects such as hysteresis of the I-V characteristics due to threshold voltage shift when the gate voltage is applied. Using gate-voltage bias stress measurements we show that a large hysteresis of up to 40V in Si NW FETs with SiO2 dielectric is mainly due to the holes traps at the nanowire/SiO2 interface. An approach for reducing this hyster…
In this letter, we explore the bandstructure effects on the performance of ballistic silicon nanowire transistors (SNWTs). The energy dispersion relations for silicon nanowires are evaluated with an sp3d5s* tight binding model. Based on the calculated dispersion relations, the ballistic currents for both n-type and p-type SNWTs are evaluated by using a semi-numerical ballistic model. For large diameter nanowires, we find that the ballistic p-SNWT delivers half the ON-current of a ballistic n-SNWT. For small diameters, however, the ON-current of the p-type SNWT approaches that of its n-type cou…
In this article, we present a configurable field-effect transistor (FET), where not only polarity (n- and p-type), but the conduction mechanism of a FET can also be configured dynamically. As a result, we can have both types of devices, high-performance MOSFET and low-power TFET, for computational and power efficient system on chip (SoC) products. The calibrated 3D-TCAD simulation results validate characteristics and functionalities of the configurable FET, and showed good consistency with the static conventional MOSFET (or TFET).
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying…
We report on the fabrication and electrical characterization at millikelvin temperatures of a novel silicon single-electron transistor (Si-SET). The island and source-drain leads of the Si-SET are formed by the implantation of phosphorus ions to a density above the metal-insulator-transition, with the tunnel junctions created by undoped regions. Surface gates above each of the tunnel junctions independently control the tunnel coupling between the Si-SET island and leads. The device shows periodic Coulomb blockade with a charging energy e$^2$/2C$_Σ$ $\sim$ 250 $μ$eV, and demonstrates a reproduc…
We investigate by low-temperature transport experiments the sub-threshold behavior of triple-gate silicon field-effect transistors. These three-dimensional nano-scale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers, down to 50x60x35 nm^3. Conductance versus gate voltage show Coulomb-blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analysis, we conclude that sub-threshol…
In this letter, we report a three-dimensional (3D) quantum mechanical simulation to investigate the effects of surface roughness scattering (SRS) on the device characteristics of Si nanowire transistors (SNWTs). We treat the microscopic structure of the Si/SiO2 interface roughness directly by using a 3D finite element technique. The results show that 1) SRS reduces the electron density of states in the channel, which increases the SNWT threshold voltage, and 2) the SRS in SNWTs becomes more effective when more propagating modes are occupied, which implies that SRS is more important in planar m…
We investigate a hybrid structure consisting of $20\pm4$ implanted $^{31}$P atoms close to a gate-induced silicon single electron transistor (SiSET). In this configuration, the SiSET is extremely sensitive to the charge state of the nearby centers, turning from the off state to the conducting state when the charge configuration is changed. We present a method to measure fast electron tunnel rates between donors and the SiSET island, using a pulsed voltage scheme and low-bandwidth current detection. The experimental findings are quantitatively discussed using a rate equation model, enabling the…
We study hole spin resonance in a p-channel silicon metal-oxide-semiconductor field-effect transistor. In the sub-threshold region, the measured source-drain current reveals a double dot in the channel. The observed spin resonance spectra agree with a model of strongly coupled two-spin states in the presence of a spin-orbit-induced anti-crossing. Detailed spectroscopy at the anti-crossing shows a suppressed spin resonance signal due to spin-orbit-induced quantum state mixing. This suppression is also observed for multi-photon spin resonances. Our experimental observations agree with theoretica…
We study single electron transport across a single Bi dopant in a Silicon Nanotransistor to assess how the strong hyperfine coupling with the Bi nuclear spin $I=9/2$ affects the transport characteristics of the device. In the sequential tunneling regime we find that at, temperatures in the range of $100 mK$, $dI/dV$ curves reflect the zero field hyperfine splitting as well as its evolution under an applied magnetic field. Our non-equilibrium quantum simulations show that nuclear spins can be partially polarized parallel or antiparallel to the electronic spin just tuning the applied bias.
In this work, we demonstrate a silicon nanocrystal Field Effect Transistor (ncFET). Its operation is similar to that of a Tunnelling Field Effect Transistor (TFET) with two barriers in series. The tunnelling barriers are fabricated in very thin silicon dioxyde and the channel in intrinsic polycrystalline silicon. The absence of doping eliminates the problem of achieving sharp doping profiles at the junctions, which has proven a challenge for large-scale integration and in principle allows scaling down the atomic level. The demonstrated ncFET features a 10$^4$ on/off current ratio at room tempe…
We have developed nano-scale double-gated field-effect-transistors for the study of electron states and transport properties of single deliberately-implanted phosphorus donors. The devices provide a high-level of control of key parameters required for potential applications in nanoelectronics. For the donors, we resolve transitions corresponding to two charge states successively occupied by spin down and spin up electrons. The charging energies and the Lande g-factors are consistent with expectations for donors in gated nanostructures.
We investigate the mechanisms responsible for the low-frequency noise in liquid-gated nano-scale silicon nanowire field-effect transistors (SiNW-FETs) and show that the charge-noise level is lower than elementary charge. Our measurements also show that ionic strength of the surrounding electrolyte has a minimal effect on the overall noise. Dielectric polarization noise seems to be at the origin of the 1/f noise in our devices. The estimated spectral density of charge noise Sq = 1.6x10-2 e/sqr(Hz) at 10 Hz opens the door to metrological studies with these SiNW-FETs for the electrical detection …
In this work, we present a quantum mechanical approach for the simulation of Si/SiO2 interface roughness scattering in silicon nanowire transistors (SNWTs). The simulation domain is discretized with a three-dimensional (3D) finite element mesh, and the microscopic structure of the Si/SiO2 interface roughness is directly implemented. The 3D Schrodinger equation with open boundary conditions is solved by the non-equilibrium Green's function method together with the coupled mode space approach. The 3D electrostatics in the device is rigorously treated by solving a 3D Poisson equation with the fin…
We demonstrate the proof of principle for a ternary adder using silicon metal-on-insulator single electron transistors (SET). Gate dependent rectifying behavior of a single electron transistor results in a robust three-valued output as a function of the potential of the SET island. Mapping logical, ternary inputs to the three gates controlling the potential of the SET island allows us to perform complex, inherently ternary operations, on a single transistor.
We explore phonon-mediated quantum transport through electronic noise characterization of a commercial CMOS transistor. The device behaves as a single electron transistor thanks to a single impurity atom in the channel. A low noise cryogenic CMOS transimpedance amplifier is exploited to perform low-frequency noise characterization down to the single electron, single donor and single phonon regime simultaneously, not otherwise visible through standard stability diagrams. Single electron tunneling as well as phonon-mediated features emerges in rms-noise measurements. Phonons are emitted at high …
We invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane based growth process monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby t…
We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10-100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared …
The effects of an atomistic interface roughness in n-type silicon nanowire transistors (SiNWT) on the radio frequency performance are analyzed. Interface roughness scattering (IRS) is statistically investigated through a three dimensional full-band quantum transport simulation based on the sp3d5s?* tight-binding model. As the diameter of the SiNWT is scaled down below 3 nm, IRS causes a significant reduction of the cut-off frequency. The fluctuations of the conduction band edge due to the rough surface lead to a reflection of electrons through mode-mismatch. This effect reduces the velocity of…
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the…
This paper examines the validity of the widely-used parabolic effective-mass approximation for computing the current-voltage (I-V) characteristics of silicon nanowire transistors (SNWTs). The energy dispersion relations for unrelaxed Si nanowires are first computed by using an sp3d5s* tight-binding model. A semi-numerical ballistic FET model is then adopted to evaluate the I-V characteristics of the (n-type) SNWTs based on both a tight-binding dispersion relation and parabolic energy bands. In comparison with the tight-binding approach, the parabolic effective-mass model with bulk effective-ma…
We demonstrate the fabrication of a single electron transistor device based on a single ultra-small silicon quantum dot connected to a gold break junction with a nanometer scale separation. The gold break junction is created through a controllable electromigration process and the individual silicon quantum dot in the junction is determined to be a Si_170 cluster. Differential conductance as a function of the bias and gate voltage clearly shows the Coulomb diamond which confirms that the transport is dominated by a single silicon quantum dot. It is found that the charging energy can be as large…
We report on room temperature THz detection by means of antenna-coupled field effect transistors fabricated by using epitaxial graphene grown on silicon carbide substrate. Two independent detection mechanisms are found: plasma wave assisted-detection and thermoelectric effect, which is ascribed to the presence of junctions along the FET channel. The superposition of the calculated functional dependence of both the plasmonic and thermoelectric photovoltages on the gate bias qualitatively well reproduces the measured photovoltages. Additionally, the sign reversal of the measured photovoltage dem…
The speed of silicon-based transistors has reached an impasse in the recent decade, primarily due to scaling techniques and the short-channel effect. Conversely, graphene (a revolutionary new material possessing an atomic thickness) has been shown to exhibit a promising value for electrical conductivity. Graphene would thus appear to alleviate some of the drawbacks associated with silicon-based transistors. It is for this reason why such a material is considered one of the most prominent candidates to replace silicon within nano-scale transistors. The major crux here, is that graphene is intri…
A large variability of carrier mobility of graphene-based field effect transistors hampers graphene science and technology. We determine the scattering strength of the dominant scatterer responsible for the variability of graphene-based transistors on silicon oxide. The strength of the scatterer is found to be more consistent with charged impurities than with resonant impurities.
Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunnelling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio-frequency resonant circuit coupled via the gate. Differential capacitan…
We invented a novel method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. BiLGFETs exhibit ultra-high on/off-current ratios of 107 at room temperature, exceeding previously reported values by several orders of magnitude. This will allow a …
A Comprehensive Study of Charge-Carrier Mobility in Double Lateral-Gate Silicon Junctionless Transistors
Laye Rooyan Part, Isfahan Science and Technology Town（拉耶鲁扬部分，伊斯法罕科技城）；Department of Physics, Isfahan University of Technology（伊斯法罕理工大学物理系）；Institute of Microengineering and Nanoelectronics, Universiti Kebangsaan Malaysia（马来西亚国立大学微工程与纳米电子研究所）；Department of Electrical and Computer Engineering, University of Texas at Dallas（德克萨斯大学达拉斯分校电气与计算机工程系）
We investigate a silicon single-electron transistor (SET) in a metal-oxide-semiconductor (MOS) structure by applying a magnetic field perpendicular to the sample surface. The quantum dot is defined electrostatically in a point contact channel and by the potential barriers from negatively charged interface traps. The magnetic field dependence of the excitation spectrum is primarily driven by the Zeeman effect. In the two-electron singlet-triplet (ST) transition, electron-electron Coulomb interaction plays a significant role. The evolution of Coulomb blockade peaks with magnetic field B is also …
A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator…
A 20 band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding (TB) model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to theoretically examine the bandstructure carrier velocity and ballistic current in silicon nanowire (NW) transistors. Infinitely long, uniform, cylindrical and rectangular NWs, of cross sectional diameters/sides ranging from 3nm to 12nm are considered. For a comprehensive analysis, n-type and p-type metal-oxide-semiconductor (NMOS and PMOS) NWs in [100], [110] and [111] transport orientations are examined. In general, physical…
A first-principle model is proposed to study the electrostatic properties of a double-gated silicon slab of nano scale in the framework of density functional theory. The applied gate voltage is approximated as a variation of the electrostatic potential on the boundary of the supercell enclosing the system. With the electron density estimated by the real space Green's functions, efficient multigrid and fast Fourier Poisson solvers are employed to calculate the electrostatic potential from the charge density. In the representation of localized SIESTA linear combination of atomic orbitals, the Ko…
Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been identified as the main source of noise at low frequency. It often originates from an ensemble of a huge number of charges trapping and detrapping. However, a deviation from the well-known model of 1/f noise is observed for nanoscale MOSFETs and a new model is required. Here, we report the observation of one-by-one trap activation controlled by the gate voltage in a nanowire MOSFET and we propose a new low-frequency-noise theory for nanoscale FETs. We demonstrate that the Coulomb repulsion between elec…
In quantum computation, information is processed by gates that must coherently couple separate qubits. In many systems the qubits are naturally coupled, but such an always-on interaction limits the algorithms that may be implemented. Coupling interactions may also be directed in devices and circuits that are provided with additional control wiring. This can be achieved by adjusting the gate voltage in a semiconductor device or an additional flux in a superconducting device. Such control signals must be applied adiabatically (limiting the speed) and the additional wiring provides pathways for n…
Semiconducting single-walled carbon nanotubes are studied in the diffusive transport regime. The peak mobility is found to scale with the square of the nanotube diameter and inversely with temperature. The maximum conductance, corrected for the contacts, is linear in the diameter and inverse temperature. These results are in good agreement with theoretical predictions for acoustic phonon scattering in combination with the unusual band structure of nanotubes. These measurements set the upper bound for the performance of nanotube transistors operating in the diffusive regime.
Radio-frequency reflectometry in silicon single-electron transistors (SETs) is presented. At low temperatures (<4 K), in addition to the expected Coulomb blockade features associated with charging of the SET dot, quasi-periodic oscillations are observed that persist in the fully depleted regime where the SET dot is completely empty. A model, confirmed by simulations, indicates that these oscillations originate from charging of an unintended floating gate located in the heavily doped polycrystalline silicon gate stack. The technique used in this experiment can be applied for detailed spectrosco…
An evaluation of the gate capacitance of a field-effect transitor (FET) whose channel length and width are several ten nanometer, is a key point for sensors applications. However, experimental and precise evaluation of capacitance in the aF range or less has been extremely difficult. Here, we report an extraction of the capacitance down to 0.55 aF for a silicon FET with a nanoscale wire channel whose width and length are 15 and 50 nm, respectively. The extraction can be achieved by using a combination of four kinds of measurements: current characteristics modulated by double gates, random-tele…
We studied transport through ultra-small Si quantum dot transistors fabricated from silicon-on-insulator wafers. At high temperatures, 4K<T<100K, the devices show single-electron or single-hole transport through the lithographically defined dot. At T<4K, current through the devices is characterized by multidot transport. From the analysis of the transport in samples with double-dot characteristics, we conclude that extra dots are formed inside the thermally grown gate oxide which surrounds the lithographically defined dot.
We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement…
Surface characterizations of an organophosphorus (OP) gas detector based on chemically functionalized silicon nanoribbon field-effect transistor (SiNR-FET) were performed by Kelvin Probe Force Microscopy (KPFM) and ToF-SIMS, and correlated with changes in the current-voltage characteristics of the devices. KPFM measurements on FETs allow (i) to investigate the contact potential difference (CPD) distribution of the polarized device as function of the gate voltage and the exposure to OP traces and, (ii) to analyze the CPD hysteresis associated to the presence of mobile ions on the surface. The C…
