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arXiv 2605.00544cond-mat.mtrl-sci
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一种基于无监督机器学习的框架用于铁电Hf0.5Zr0.5O2薄膜电容器晶片级变异性分析与性能预测

An Unsupervised Machine Learning-based Framework for Wafer Scale Variability Analysis and Performance Prediction of Ferroelectric Hf0.5Zr0.5O2 Thin Film Capacitors

Tampere University(坦佩雷大学)

Anika Anu, Sayani Majumdar

AI总结:

本文提出利用PCA和K-means聚类分析HZO电容器的晶片内设备间变异性,通过虚拟计量方法预测未测试设备性能,MAPE在5-10%范围内,有效提升良率并减少计量开销。

摘要:

制造过程诱导的性能变异性仍是半导体芯片高产量制造中的重大障碍。随着人工智能工作负载的激增,对非易失性和计算记忆的需求呈指数增长。作为嵌入式非易失性存储器,铁电Hf0.5Zr0.5O2因其与CMOS后端(BEOL)的兼容性、可扩展性和高性能而成为有力候选。然而,其敏感的晶化动力学导致显著的设备间(D2D)非均匀性,导致晶片级性能的不可预测性。本文演示无监督机器学习可以分析晶片内D2D变化并高效预测“未见过”的设备性能。我们提出一个框架,利用主成分分析(PCA)和K-均值聚类分析HZO电容器的D2D性能变化,并基于多个晶片的数据,超越传统描述性统计,采用预测的“虚拟计量”方法,根据关键参数如剩余极化(Pr)和矫顽电压(Vc)定义性能类别。分析进一步扩展到比较晶片上不同晶片的均匀性,显示所提出的方法能够准确预测未测试晶片的设备性能,MAPE在5-10%范围内,表明了一条稳健的加速良率改进和减少计量开销的路径。

英文摘要:

Fabrication process-induced performance variability remains a formidable barrier in the high-volume manufacturing of semiconductor chips. With skyrocketing Artificial Intelligence (AI) workload, demand for non-volatile and computational memories is growing exponentially. As embedded non-volatile memory, ferroelectric Hf0.5Zr0.5O2 emerged as a strong candidate due to their CMOS back-end-of-line (BEOL) compatibility, scalability and high performance. However, their sensitive crystallization kinetics leads to significant device-to-device (D2D) non-uniformity leading to unpredictability of performance over wafer scale. In this work, we demonstrate unsupervised machine learning can analyze intra-die D2D variations and predict performance of "unseen" dies efficiently. We present a framework utilizing Principal Component Analysis (PCA) and K-Means clustering to analyze D2D performance variations in HZO capacitors and building on data from multiple dies, we move beyond traditional descriptive statistics to a predictive "Virtual Metrology" approach that separates performance categories, defined by key parameters like remanent polarization (Pr) and coercive voltage (Vc). The analysis further extends to comparing uniformity across different dies across the wafer showing the proposed methodology can accurately predict device performance on untested dies with a low Mean Absolute Percentage Error (MAPE) in the range of 5-10%, suggesting a robust path for accelerated yield improvement and reduced metrology overhead.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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