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arXiv 2409.08096cond-mat.mtrl-scicond-mat.mes-hallphysics.app-ph
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面向未来CMOS技术节点的亚1纳米厚度氧化物半导体的从头算器件驱动筛选

Ab Initio Device-Driven Screening of Sub-1-nm Thickness Oxide Semiconductors for Future CMOS Technology Nodes

Linqiang Xu, Yue Hu, Lianqiang Xu, Lin Xu, Qiuhui Li, Aili Wang, Chit Siong Lau, Jing Lu, Yee Sin Ang

AI总结:

针对超薄氧化物半导体多为n型、难以适配CMOS技术的问题,本研究开发从头算器件驱动筛选流程,发现CaO、SrO等亚1nm氧化物可同时满足ITRS的n/p型器件高性能与低功耗标准,拓宽了未来CMOS的候选材料范围。

摘要:

亚1纳米厚度的超薄氧化物半导体因具备抗短沟道效应、高空气稳定性以及低能耗器件运行潜力,是超缩尺寸场效应晶体管(FET)应用的极具前景的构建模块。然而,超薄氧化物FET的n型主导特性阻碍了其向互补金属-氧化物-半导体(CMOS)技术的集成,而CMOS技术需要同时具备n型和p型器件。本文开发了一套从头算的器件驱动计算筛选工作流,用于识别适用于亚5纳米FET应用的亚1纳米厚度氧化物半导体。研究表明,超薄CaO₂、CaO和SrO在国际半导体技术路线图(ITRS)规定的高性能(HP)和低功耗(LP)两种要求下,均能兼容p型器件运行,从而拓展了目前数量有限的p型氧化物半导体家族。值得注意的是,CaO和SrO成为首批能够同时满足ITRS的HP和LP标准、且同时适配n型和p型器件的亚1纳米厚度氧化物半导体。CaO和SrO基FET的性能优于许多现有低维半导体,展现出5纳米栅长以下的可缩尺寸性。本研究成果是亚1纳米厚度氧化物半导体的从头算、器件驱动筛选领域的开创性工作,显著拓宽了未来CMOS技术节点的候选材料库。

英文摘要:

Ultrathin oxide semiconductors with sub-1-nm thickness are promising building blocks for ultrascaled field-effect transistor (FET) applications due to their resilience against short-channel effects, high air stability, and potential for low-energy device operation. However, the n-type dominance of ultrathin oxide FET has hindered their integration into complementary metal-oxide-semiconductor (CMOS) technology, which requires both n-and p-type devices. Here we develop an ab initio device-driven computational screening workflow to identify sub-1-nm thickness oxide semiconductors for sub-5-nm FET applications. We demonstrate that ultrathin CaO2, CaO, and SrO are compatible with p-type device operations under both high-performance (HP) and low-power (LP) requirements specified by the International Technology Roadmap of Semiconductors (ITRS), thereby expanding the limited family of p-type oxide semiconductors. Notably, CaO and SrO emerge as the first-of-kind sub-1-nm thickness oxide semiconductors capable of simultaneously meeting the ITRS HP and LP criteria for both n-and p-type devices. CaO and SrO FETs outperform many existing low-dimensional semiconductors, exhibiting scalability below 5-nm gate length. Our findings offer a pioneering effort in the ab initio, device-driven screening of sub-1-nm thickness oxide semiconductors, significantly broadening the material candidate pool for future CMOS technology nodes.

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