AI 中文总结
本研究实现200毫米晶圆级三层ALD InOx基器件的M3D集成，开发四层三维存算一体加速器，为下一代AI硬件提供可扩展且兼容CMOS的平台。
AI 中文摘要
单片三维（M3D）集成通过多功能逻辑与存储器件的密集垂直堆叠，为突破传统硅互补金属氧化物半导体（CMOS）技术的缩放极限提供了可行路径。本研究在200毫米硅晶圆上实现了三层原子层沉积（ALD）氧化铟（InOx）基器件的晶圆级M3D集成，共制备超过10万个器件，涵盖铁电型、增强型及耗尽型场效应晶体管。研究获得低至0.04V的阈值电压标准差、最高达91.6 cm²V⁻¹s⁻¹的平均电子迁移率，且实现了全功能跨层电路。采用定制InOx工艺设计套件开发了面向大语言模型 workload的四层三维存算一体（CIM）加速器，相比二维基线实现1.4倍至2.9倍的加速比及相当的能量延迟乘积提升。上述结果确立了ALD InOx M3D集成为可扩展、兼容CMOS的平台，可用于下一代人工智能硬件及先进电子器件。
英文摘要
Monolithic 3D (M3D) integration offers a pathway to overcome the scaling limits of conventional silicon complementary metal-oxide-semiconductor (CMOS) technology by extending dense vertical stacking of multifunctional logic and memory devices. Here, we demonstrate wafer-scale M3D integration of three tiers of atomic-layer-deposited (ALD) indium oxide (InOx)-based devices (>100,000 fabricated), including ferroelectric, enhancement-mode, and depletion-mode field-effect transistors, on 200 mm silicon wafers. We achieve threshold voltage standard deviation as low as 0.04 V, average electron mobility up to 91.6 cm2V-1s-1, and fully functional cross-tier circuits. A four-tier 3D computing-in-memory (CIM) accelerator targeting large language model workloads is developed using a custom InOx process design kit, delivering 1.4x to 2.9x speedup and comparable energy-delay product improvements over 2D baselines. These results establish ALD InOx M3D integration as a scalable and CMOS-compatible platform for next-generation artificial intelligence hardware and advanced electronics.
