The typical time-independent view of quantum error correction (QEC) codes hides significant freedom in the decomposition into circuits that are executable on hardware. Using the concept of detecting regions, we design time-dynamic QEC circuits directly instead of designing static QEC codes to decompose into circuits. In particular, we improve on the standard circuit constructions for the surface code, presenting new circuits that can embed on a hexagonal grid instead of a square grid, that can use ISWAP gates instead of CNOT or CZ gates, that can exchange qubit data and measure roles, and that move logical patches around the physical qubit grid while executing. All these constructions use no additional entangling gate layers and display essentially the same logical performance, having teraquop footprints within 25% of the standard surface code circuit. We expect these circuits to be of great interest to quantum hardware engineers, because they achieve essentially the same logical performance as standard surface code circuits while relaxing demands on hardware.
We focus on the depth optimization of CNOT circuits on hardwares with limited connectivity. We adapt the algorithm from Kutin et al. that implements any $n$-qubit CNOT circuit in depth at most $5n$ on a Linear Nearest Neighbour (LNN) architecture. Our proposal is a block version of Kutin et al.'s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have the less the depth. We derive better theoretical upper bounds and we provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on so…
Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed b…
As the nascent field of quantum computing develops, an increasing number of quantum hardware modalities, such as superconducting electronic circuits, semiconducting spins, trapped ions, and neutral atoms, have become available for performing quantum computations. These quantum hardware modalities exhibit varying characteristics and implement different universal quantum gate sets that may e.g. contain several distinct two-qubit quantum gates. Adapting a quantum circuit from a, possibly hardware-agnostic, universal quantum gate set to the quantum gate set of a target hardware modality has a cruc…
Alternating ZX Circuit Extraction for Hardware-Adaptive Compilation
Technical University of Munich（慕尼黑工业大学）；Ludwig-Maximilians-University Munich（慕尼黑大学）；Software Competence Center Hagenberg GmbH（哈根堡软件能力中心有限公司）；Munich Quantum Software Company GmbH（慕尼黑量子软件公司有限公司）
Beyond Logical Circuits: Hardware-Aware Analysis of Expressibility and Trainability in Variational Quantum Algorithms
Division of Engineering, New York University Abu Dhabi (NYUAD)（纽约大学阿布扎比分校工程学院）；Center for Quantum and Topological Systems (CQTS), NYUAD Research Institute, NYUAD（纽约大学阿布扎比分校研究院量子与拓扑系统中心）
We show a pulse-efficient circuit transpilation framework for noisy quantum hardware. This is achieved by scaling cross-resonance pulses and exposing each pulse as a gate to remove redundant single-qubit operations with the transpiler.Crucially, no additional calibration is needed to yield better results than a CNOT-based transpilation. This pulse-efficient circuit transpilation therefore enables a better usage of the finite coherence time without requiring knowledge of pulse-level details from the user. As demonstration, we realize a continuous family of cross-resonance-based gates for SU(4) …
Late Breaking Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits
eBRAIN Lab, Division of Engineering, New York University (NYU) Abu Dhabi（纽约大学阿布扎比分校工程学院）；Center for Quantum and Topological Systems, NYUAD Research Institute, NYU Abu Dhabi（纽约大学阿布扎比分校研究学院量子与拓扑系统中心）
Quantum walks are a promising framework for developing quantum algorithms and quantum simulations. They represent an important test case for the application of quantum computers. Here we present different forms of discrete-time quantum walks (DTQWs) and show their equivalence for physical realizations. Using an appropriate digital mapping of the position space on which a walker evolves to the multiqubit states of a quantum processor, we present different configurations of quantum circuits for the implementation of DTQWs in one-dimensional position space. We provide example circuits for a five-…
Circuit Depth Reduction for Executable Hamiltonian Dynamics of Covalent Inhibitor Reactivity on Quantum Hardware
Capgemini Quantum Lab（凯捷量子实验室）；IBM T. J. Watson Research Center（IBM T.J.沃森研究中心）；Haiqu Inc.（海奇公司）；IBM Quantum IBM France Lab（IBM量子法国实验室）；GSK Medicines Research Centre（葛兰素史克药物研究中心）
We introduce a framework for the calculation of ground and excited state energies of bosonic systems suitable for near-term quantum devices and apply it to molecular vibrational anharmonic Hamiltonians. Our method supports generic reference modal bases and Hamiltonian representations, including the ones that are routinely used in classical vibrational structure calculations. We test different parametrizations of the vibrational wave function, which can be encoded in quantum hardware, based either on heuristic circuits or on the bosonic Unitary Coupled Cluster Ansatz. In particular, we define a…
Shallow instantaneous quantum polynomial-time circuits for generative modeling on noisy intermediate-scale quantum hardware
Eurecat, Centre Tecnològic de Catalunya（Eurecat，加泰罗尼亚技术中心）；Centre de Visió per Computador (CVC)（计算机视觉中心）；Universitat Autònoma de Barcelona (UAB)（巴塞罗那自治大学）
IQPopt: Fast optimization of instantaneous quantum polynomial circuits in JAX
ICFO-Institut de Ciencies Fotoniques, The Barcelona Institute of Science and Technology（ICFO-光子科学研究所，巴塞罗那科学技术研究所）；Eurecat, Centre Tecnològic de Catalunya（Eurecat，加泰罗尼亚技术中心）；Xanadu
From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware
School of Computing and Information Systems, Singapore Management University（新加坡管理大学计算与信息系）；Institute of High Performance Computing, A*STAR（A*STAR高性能计算研究所）
Following the simple observation that the interconnection of a set of quantum optical input-output devices can be specified using structural mode VHSIC Hardware Description Language (VHDL), we demonstrate a computer-aided schematic capture workflow for modeling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.
Here we present qFlex, a flexible tensor network based quantum circuit simulator. qFlex can compute both exact amplitudes, essential for the verification of the quantum hardware, as well as low fidelity amplitudes, in order to mimic sampling from Noisy Intermediate-Scale Quantum (NISQ) devices. In this work, we focus on random quantum circuits (RQCs) in the range of sizes expected for supremacy experiments. Fidelity $f$ simulations are performed at a cost that is $1/f$ lower than perfect fidelity ones. We also present a technique to eliminate the overhead introduced by rejection sampling in mo…
Quantum measurement is important to quantum computing as it extracts the outcome of the circuit at the end of the computation. Previously, all measurements have to be done at the end of the circuit. Otherwise, it will incur significant errors. But it is not the case now. Recently IBM started supporting dynamic circuits through hardware (instead of software by simulator). With mid-circuit hardware measurement, we can improve circuit efficacy and fidelity from three aspects: (a) reduced qubit usage, (b) reduced swap insertion, and (c) improved fidelity. We demonstrate this using real-world appli…
Quantum circuit simulators have a long tradition of exploiting massive hardware parallelism. Most of the times, parallelism has been supported by special purpose libraries tailored specifically for the quantum circuits. Quantum circuit simulators are integral part of quantum software stacks, which are mostly written in Python. Our focus has been on ease of use, implementation and maintainability within the Python ecosystem. We report the performance gains we obtained by using CuPy, a general purpose library (linear algebra) developed specifically for CUDA-based GPUs, to simulate quantum circui…
For efficient hardware-accelerated simulations of quantum circuits, we can define hardware-specific quantum-circuit transformations. We use a functional programming approach to create a quantum-circuit analysis and transformation method implemented in Haskell. This tool forms a key part of our larger quantum-computing simulation toolchain. As an example of hardware acceleration, we discuss FPGA-based simulations of selected quantum arithmetic circuits, including the transformation steps to optimise the hardware utilisation. Future development steps in the Haskell-based analysis and transformat…
The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurem…
The failure susceptibility of the quantum hardware will force quantum computers to execute fault-tolerant quantum circuits. These circuits are based on quantum error correcting codes, and there is increasing evidence that one of the most practical choices is the surface code. Design methodologies of surface code based quantum circuits were focused on the layout of such circuits without emphasizing the reduced availability of hardware and its effect on the execution time. Circuit layout has not been investigated for practical scenarios, and the problem presented herein was neglected until now. …
Quantum computing is performed on Noisy Intermediate-Scale Quantum (NISQ) hardware in the short term. Only small circuits can be executed reliably on a quantum machine due to the unavoidable noisy quantum operations on NISQ devices, leading to the under-utilization of hardware resources. With the growing demand to access quantum hardware, how to utilize it more efficiently while maintaining output fidelity is becoming a timely issue. A parallel circuit execution technique has been proposed to address this problem by executing multiple programs on hardware simultaneously. It can improve the har…
Application-inspired benchmarks measure how well a quantum device performs meaningful calculations. In the case of parameterized circuit training, the computational task is the preparation of a target quantum state via optimization over a loss landscape. This is complicated by various sources of noise, fixed hardware connectivity, and for generative modeling, the choice of target distribution. Gradient-based training has become a useful benchmarking task for noisy intermediate scale quantum computers because of the additional requirement that the optimization step uses the quantum device to es…
