The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.
Quantum computers may provide good solutions to combinatorial optimization problems by leveraging the Quantum Approximate Optimization Algorithm (QAOA). The QAOA is often presented as an algorithm for noisy hardware. However, hardware constraints limit its applicability to problem instances that closely match the connectivity of the qubits. Furthermore, the QAOA must outpace classical solvers. Here, we investigate swap strategies to map dense problems into linear, grid and heavy-hex coupling maps. A line-based swap strategy works best for linear and two-dimensional grid coupling maps. Heavy-he…
Quantum computers are currently accessible through a cloud-based platform that allows users to run their programs on a suite of quantum hardware. As the quantum computing ecosystem grows in popularity and utility, it is reasonable to expect more companies, including untrustworthy or untrustworthy or unreliable vendors, to begin offering quantum computers as hardware as a service at various price or performance points. Since computing time on quantum hardware is expensive and the access queue may be long, users will be enticed to use less expensive but less reliable or trustworthy hardware. Les…
Given $N_{\textrm{tot}}$ applications of a unitary operation with an unknown phase $θ$, a large-scale fault-tolerant quantum system can {reduce} an estimate's {error} scaling from $\mathcal{O} \left[ 1 / \sqrt{N_{\textrm{tot}}} \right]$ to $\mathcal{O} \left[ 1 / {N_{\textrm{tot}}} \right]$. Owing to the limited resources available to near-term quantum devices, entanglement-free protocols have been developed, which achieve a $\mathcal{O} \left[ \log(N_{\textrm{tot}}) / N_{\textrm{tot}} \right]$ {mean-absolute-error} scaling. Here, we propose a new two-step protocol for near-term phase estimati…
We propose a general framework for quantum error mitigation that combines and generalizes two techniques: probabilistic error cancellation (PEC) and zero-noise extrapolation (ZNE). Similarly to PEC, the proposed method represents ideal operations as linear combinations of noisy operations that are implementable on hardware. However, instead of assuming a fixed level of hardware noise, we extend the set of implementable operations by noise scaling. By construction, this method encompasses both PEC and ZNE as particular cases and allows us to investigate a larger set of hybrid techniques. For ex…
Evaluating the Quantum Approximate Optimization Algorithms for QUBO problems Across Quantum Hardware Platforms: Performance Analysis, Challenges, and Strategies
University of Oulu（奥卢大学）；Indian Institute of Science（印度科学学院）；OP Financial Group（OP金融集团）
Transition from Statistical to Hardware-Limited Scaling in Photonic Quantum State Reconstruction
Institute for Physics and Astronomy, Eötvös Loránd University（罗兰大学物理与天文学研究所）；Institute for Solid State Physics and Optics, HUN-REN Wigner Research Centre for Physics（匈牙利研究与教育网络温格物理研究中心固态物理与光学研究所）
In order to treat all-to-all connected quadratic binary optimization problems (QUBO) with hardware quantum annealers, an embedding of the original problem is required due to the sparsity of the hardware's topology. Embedding fully-connected graphs - typically found in industrial applications - incurs a quadratic space overhead and thus a significant overhead in the time to solution. Here we investigate this embedding penalty of established planar embedding schemes such as minor embedding on a square lattice, minor embedding on a Chimera graph, and the Lechner-Hauke-Zoller scheme using simulate…
With current semiconductor technology reaching its physical limits, special-purpose hardware has emerged as an option to tackle specific computing-intensive challenges. Optimization in the form of solving Quadratic Unconstrained Binary Optimization (QUBO) problems, or equivalently Ising spin glasses, has been the focus of several new dedicated hardware platforms. These platforms come in many different flavors, from highly-efficient hardware implementations on digital-logic of established algorithms to proposals of analog hardware implementing new algorithms. In this work, we use a mapping of a…
Existing protocols for benchmarking current quantum co-processors fail to meet the usual standards for assessing the performance of High-Performance-Computing platforms. After a synthetic review of these protocols -- whether at the gate, circuit or application level -- we introduce a new benchmark, dubbed Atos Q-score (TM), that is application-centric, hardware-agnostic and scalable to quantum advantage processor sizes and beyond. The Q-score measures the maximum number of qubits that can be used effectively to solve the MaxCut combinatorial optimization problem with the Quantum Approximate Op…
Maximum-Likelihood Amplitude Estimation for Quantum Monte Carlo Integration on Trapped-Ion Hardware: Convergence, Noise-Floor Saturation, Depth-Dependent Bias
BosonQ Psi Corp（BosonQ Psi 公司）；National Quantum Laboratory (QLab), University of Maryland, College Park（马里兰大学国家量子实验室（QLab））
In this paper, we present QPack, a universal benchmark for Noisy Intermediate-Scale Quantum (NISQ) computers based on Quantum Approximate Optimization Algorithms (QAOA). Unlike other evaluation metrics in the field, this benchmark evaluates not only one, but multiple important aspects of quantum computing hardware: the maximum problem size a quantum computer can solve, the required runtime, as well as the achieved accuracy. The applications MaxCut, dominating set and traveling salesman are included to provide variation in resource requirements. This will allow for a diverse benchmark that prom…
The scaling up of quantum hardware is the fundamental challenge ahead in order to realize the disruptive potential of quantum technology in information science. Among the plethora of hardware platforms, photonics stands out by offering a modular approach, where the main challenge is to construct sufficiently high-quality building blocks and develop methods to efficiently interface them. Importantly, the subsequent scaling-up will make full use of the mature integrated photonic technology provided by photonic foundry infrastructure to produce small foot-print quantum processors of immense compl…
We present methods for constructing any target coupling graph using limited global controls in an Ising-like quantum spin system. Our approach is motivated by implementing the quantum approximate optimization algorithm (QAOA) on trapped ion quantum hardware to find approximate solutions to Max-Cut. We present a mathematical description of the problem and provide approximately optimal algorithmic constructions that generate arbitrary unweighted coupling graphs with $n$ nodes in $O(n)$ global entangling operations and weighted graphs with $m$ edges in $O(m)$ operations. These upper bounds are no…
Recent assertions of a potential advantage of Quantum Neural Network (QNN) for specific Machine Learning (ML) tasks have sparked the curiosity of a sizable number of application researchers. The parameterized quantum circuit (PQC), a major building block of a QNN, consists of several layers of single-qubit rotations and multi-qubit entanglement operations. The optimum number of PQC layers for a particular ML task is generally unknown. A larger network often provides better performance in noiseless simulations. However, it may perform poorly on hardware compared to a shallower network. Because …
A Backend-Agnostic MWIS Kernel for Stochastic Unit Commitment with Neutral-Atom Hardware Validation
University of Cambridge（剑桥大学）；China Mobile (Suzhou) Software Technology Co., Ltd.（中国移动（苏州）软件技术有限公司）；Taiyi Quantum Science & Technology Co. Ltd.（太一量子科技有限公司）
Toward quantum scaling advantage in approximate optimization
Wrocław University of Science and Technology（弗罗茨瓦夫理工大学）；Quantumz.io Sp. z o.o.（Quantumz.io有限责任公司）；University of Gdańsk（格但斯克大学）；Polish Academy of Sciences（波兰科学院）
Materials simulations involving strongly correlated electrons pose fundamental challenges to state-of-the-art electronic structure methods but are hypothesized to be the ideal use case for quantum computing. To date, no quantum computer has simulated a molecule of a size and complexity relevant to real-world applications, despite the fact that the variational quantum eigensolver (VQE) algorithm can predict chemically accurate total energies. Nevertheless, because of the many applications of moderately-sized, strongly correlated systems, such as molecular catalysts, the successful use of the VQ…
Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for trapping and cooling the ion qubits, stabilizing the optical frequency combs used to dri…
An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification…
Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardw…
It is shown that the energy levels of the one-dimensional nonlinear Schrodinger, or Gross-Pitaevskii, equation with the homogeneous trap potential $x^{2p}$, $p\geq 1$, obey an approximate scaling law and as a consequence the energy increases approximately linearly with the quantum number. Moreover, for a quadratic trap, $p=1$, the rate of increase of energy with the quantum number is independent of the nonlinearity: this prediction is confirmed with numerical calculations. It is also shown that the energy levels computed using a variational approximation do not satisfy this scaling law.
