AI 中文总结
该研究针对模块化三维玻色量子处理器，对比三类架构的缩放权衡，建立系统评估框架，为相关硬件设计提供器件级参数依据。
AI 中文摘要
我们提出一种模块化三维玻色量子处理器，由可重复的耦合腔模块构成，这些模块通过可配置的互连网络连接。利用受硬件驱动的图论度量，我们从互连数量、通信距离、资源集中程度和实现复杂度等方面，对比了近邻型、基于枢纽型和混合型架构。我们的分析并未确定普遍最优的拓扑结构，而是展示了这些架构如何重新分配缩放的成本，包括布线与端口需求、非局域通信距离、对共享资源的依赖、路由瓶颈以及调度开销。对3×3处理器和更大规模的分层架构的案例研究，进一步区分了有限尺寸性能与渐近缩放特性。所提出的框架为评估模块化三维玻色处理器，以及确定定量硬件设计所需的器件级参数，提供了系统基础。
英文摘要
We propose a modular three-dimensional bosonic quantum processor built from repeatable coupled-cavity modules linked by configurable interconnect networks. Using hardware-motivated graph-theoretic measures, we compare nearest-neighbor, hub-based, and hybrid architectures in terms of interconnect count, communication distance, resource concentration, and implementation complexity. Rather than identifying a universally optimal topology, our analysis shows how these architectures redistribute the costs of scaling, including wiring and port requirements, nonlocal communication distance, exposure to shared resources, routing bottlenecks, and scheduling overhead. Case studies of a \(3\times3\) processor and a larger hierarchical architecture further distinguish finite-size performance from asymptotic scaling. The resulting framework provides a systematic basis for evaluating modular three-dimensional bosonic processors and for identifying the device-level parameters required for quantitative hardware design.
