Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.
We focus on the depth optimization of CNOT circuits on hardwares with limited connectivity. We adapt the algorithm from Kutin et al. that implements any $n$-qubit CNOT circuit in depth at most $5n$ on a Linear Nearest Neighbour (LNN) architecture. Our proposal is a block version of Kutin et al.'s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have the less the depth. We derive better theoretical upper bounds and we provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on so…
As the nascent field of quantum computing develops, an increasing number of quantum hardware modalities, such as superconducting electronic circuits, semiconducting spins, trapped ions, and neutral atoms, have become available for performing quantum computations. These quantum hardware modalities exhibit varying characteristics and implement different universal quantum gate sets that may e.g. contain several distinct two-qubit quantum gates. Adapting a quantum circuit from a, possibly hardware-agnostic, universal quantum gate set to the quantum gate set of a target hardware modality has a cruc…
We show a pulse-efficient circuit transpilation framework for noisy quantum hardware. This is achieved by scaling cross-resonance pulses and exposing each pulse as a gate to remove redundant single-qubit operations with the transpiler.Crucially, no additional calibration is needed to yield better results than a CNOT-based transpilation. This pulse-efficient circuit transpilation therefore enables a better usage of the finite coherence time without requiring knowledge of pulse-level details from the user. As demonstration, we realize a continuous family of cross-resonance-based gates for SU(4) …
Late Breaking Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits
eBRAIN Lab, Division of Engineering, New York University (NYU) Abu Dhabi（纽约大学阿布扎比分校工程学院）；Center for Quantum and Topological Systems, NYUAD Research Institute, NYU Abu Dhabi（纽约大学阿布扎比分校研究学院量子与拓扑系统中心）
The mapping of quantum circuits to qubits represented by ion states in a storage ring quantum computer is examined. Serial, parallel and hybrid architectures for mapping such qubits onto a storage ring quantum computer are presented. Parallelism is an important part of the SRQC architecture in terms of multiple ions, windows and lasers. A "predecessor problem" that arises in such architectures is identified and a solution is proposed. Representative numerical sizing and timing calculations are presented. The entire methodology is very general and extends to several implementation options. Open…
Quantum walks are a promising framework for developing quantum algorithms and quantum simulations. They represent an important test case for the application of quantum computers. Here we present different forms of discrete-time quantum walks (DTQWs) and show their equivalence for physical realizations. Using an appropriate digital mapping of the position space on which a walker evolves to the multiqubit states of a quantum processor, we present different configurations of quantum circuits for the implementation of DTQWs in one-dimensional position space. We provide example circuits for a five-…
Circuit Depth Reduction for Executable Hamiltonian Dynamics of Covalent Inhibitor Reactivity on Quantum Hardware
Capgemini Quantum Lab（凯捷量子实验室）；IBM T. J. Watson Research Center（IBM T.J.沃森研究中心）；Haiqu Inc.（海奇公司）；IBM Quantum IBM France Lab（IBM量子法国实验室）；GSK Medicines Research Centre（葛兰素史克药物研究中心）
We introduce a framework for the calculation of ground and excited state energies of bosonic systems suitable for near-term quantum devices and apply it to molecular vibrational anharmonic Hamiltonians. Our method supports generic reference modal bases and Hamiltonian representations, including the ones that are routinely used in classical vibrational structure calculations. We test different parametrizations of the vibrational wave function, which can be encoded in quantum hardware, based either on heuristic circuits or on the bosonic Unitary Coupled Cluster Ansatz. In particular, we define a…
The quantum circuit mapping approach is an indispensable part of the software stack for the noisy intermediatescale quantum (NISQ) device. It has a significant impact on the reliability of computational tasks on NISQ devices. To improve the overall fidelity of physical circuits, we propose a quantum circuit mapping method based on multi-agent cooperation. This approach considers the Spatio-temporal variation of quantum operation quality on the NISQ device when inserting ancillary operation. It consists of two core components: the qubit placement algorithm and the qubit routing method. The qubi…
Current quantum annealing (QA) hardware suffers from practical limitations such as finite temperature, sparse connectivity, small qubit numbers, and control error. We propose new algorithms for mapping boolean constraint satisfaction problems (CSPs) onto QA hardware mitigating these limitations. In particular we develop a new embedding algorithm for mapping a CSP onto a hardware Ising model with a fixed sparse set of interactions, and propose two new decomposition algorithms for solving problems too large to map directly into hardware. The mapping technique is locally-structured, as hardware c…
Rapid advancement in the domain of quantum technologies has opened up researchers to the real possibility of experimenting with quantum circuits and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise poses a challenge in the smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate…
From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware
School of Computing and Information Systems, Singapore Management University（新加坡管理大学计算与信息系）；Institute of High Performance Computing, A*STAR（A*STAR高性能计算研究所）
We present a scalable set of universal gates and multiply controlled gates in a qudit basis through a bijective mapping from N qubits to qudits with D = 2^N levels via rotations in U(2). For each of the universal gates (H, CNOT, and T), as well as the NOT gate and multiply-controlled-Z gates, we describe a systematic approach to identifying the set of U(2) rotations required to implement each gate for any qudit of size N and with minimal use of an ancilla level. The qudit gates are analyzed in terms of the total rotation count and gate depth as the system scales with D. We apply the qudit-basi…
Following the simple observation that the interconnection of a set of quantum optical input-output devices can be specified using structural mode VHSIC Hardware Description Language (VHDL), we demonstrate a computer-aided schematic capture workflow for modeling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.
Here we present qFlex, a flexible tensor network based quantum circuit simulator. qFlex can compute both exact amplitudes, essential for the verification of the quantum hardware, as well as low fidelity amplitudes, in order to mimic sampling from Noisy Intermediate-Scale Quantum (NISQ) devices. In this work, we focus on random quantum circuits (RQCs) in the range of sizes expected for supremacy experiments. Fidelity $f$ simulations are performed at a cost that is $1/f$ lower than perfect fidelity ones. We also present a technique to eliminate the overhead introduced by rejection sampling in mo…
Quantum measurement is important to quantum computing as it extracts the outcome of the circuit at the end of the computation. Previously, all measurements have to be done at the end of the circuit. Otherwise, it will incur significant errors. But it is not the case now. Recently IBM started supporting dynamic circuits through hardware (instead of software by simulator). With mid-circuit hardware measurement, we can improve circuit efficacy and fidelity from three aspects: (a) reduced qubit usage, (b) reduced swap insertion, and (c) improved fidelity. We demonstrate this using real-world appli…
Quantum algorithms need to be compiled to respect the constraints imposed by quantum processors, which is known as the mapping problem. The mapping procedure will result in an increase of the number of gates and of the circuit latency, decreasing the algorithm's success rate. It is crucial to minimize mapping overhead, especially for Noisy Intermediate-Scale Quantum (NISQ) processors that have relatively short qubit coherence times and high gate error rates. Most of prior mapping algorithms have only considered constraints such as the primitive gate set and qubit connectivity, but the actual g…
Quantum circuit simulators have a long tradition of exploiting massive hardware parallelism. Most of the times, parallelism has been supported by special purpose libraries tailored specifically for the quantum circuits. Quantum circuit simulators are integral part of quantum software stacks, which are mostly written in Python. Our focus has been on ease of use, implementation and maintainability within the Python ecosystem. We report the performance gains we obtained by using CuPy, a general purpose library (linear algebra) developed specifically for CUDA-based GPUs, to simulate quantum circui…
For efficient hardware-accelerated simulations of quantum circuits, we can define hardware-specific quantum-circuit transformations. We use a functional programming approach to create a quantum-circuit analysis and transformation method implemented in Haskell. This tool forms a key part of our larger quantum-computing simulation toolchain. As an example of hardware acceleration, we discuss FPGA-based simulations of selected quantum arithmetic circuits, including the transformation steps to optimise the hardware utilisation. Future development steps in the Haskell-based analysis and transformat…
The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurem…
We introduce an error mitigation framework that mitigates errors in a quantum circuit using circuit cutting. Our framework can be implemented in polynomial time for a wide variety of quantum circuits. Our technique involves cutting the circuit in such a way that we run the circuit that needs to be executed on the quantum hardware whereas the error mitigation circuit is run on a simulator. We perform error mitigation qubit by qubit and then provide a way to combine the different probabilities from each of the individual qubit error mitigation runs such that the full circuit is error mitigated. …
The failure susceptibility of the quantum hardware will force quantum computers to execute fault-tolerant quantum circuits. These circuits are based on quantum error correcting codes, and there is increasing evidence that one of the most practical choices is the surface code. Design methodologies of surface code based quantum circuits were focused on the layout of such circuits without emphasizing the reduced availability of hardware and its effect on the execution time. Circuit layout has not been investigated for practical scenarios, and the problem presented herein was neglected until now. …
