Ferroelectric tunnel junction devices based on ferroelectric thin films of solid solutions of hafnium dioxide can enable CMOS integration of ultra-low power ferroelectric devices with potential for memory and emerging computing schemes such as in-memory computing and neuromorphic applications. In this work, we present ferroelectric tunnel junctions based on Hf$_{0.5}$Zr$_{0.5}$O$_{2}$ with materials and processes compatible with CMOS back-end-of-line integration. We show a device architecture based on W-Hf$_{0.5}$Zr$_{0.5}$O$_{2}$-Al$_{2}$O$_{3}$-TiN stacks featuring low temperature annealing at 400°C with performance comparable to those obtained with higher temperature annealing conditions.
We report a complementary metal oxide semiconductor (CMOS) technology compatible ferroelectric tunnel junction memristor grown directly on top of a Silicon substrate using a scandium doped aluminum nitride as the ferroelectric layer.
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memo…
Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classic…
My research is dedicated to the electronic properties of functional oxides. My activity specifically focuses on ferroelectric tunnel junctions in which an ultrathin layer of ferroelectric material is intercalated between two metallic electrodes. In these devices, polarization reversal induces large modifications of the tunnel resistance, leading to a non-destructive readout of the information. After a demonstration of the concept with scanning probe microscopy techniques, I have been exploring the properties of ferroelectric tunnel junctions with various ferroelectric materials (BaTiO3, BiFeO3…
We report on the fabrication of organic multiferroic tunnel junction (OMFTJ) based on an organic barrier of Poly(vinylidene fluoride) (PVDF):Fe3O4 nanocomposite. By adding Fe3O4 nanoparticles into the PVDF barrier, we found that the ferroelectric properties of the OMFTJ are considerably improved compared to that with pure PVDF barrier. It can lead to a tunneling electroresistance (TER) of about 450% at 10K and 100% at room temperature (RT), which is much higher than that of the pure PVDF based device (70% at 10K and 7% at RT). OMFTJs based on the PVDF:Fe3O4 nanocomposite could open new functio…
A ferroelectric tunnel barrier in between two ferromagnetic electrodes (multiferroic tunnel junction, MFTJ), is one of the most promising concepts for future microelectronic devices. In parallel, Hafnia based ferroelectrics are showing great potential for device miniaturization down to the nanoscale. Here we utilize ferroelectric Hf0.5Zr0.5O2 (HZO) with thickness of only 2 nm, epitaxially grown on La0.7Sr0.3MnO3 (LSMO) ferromagnetic electrodes, as a large band-gap insulating barrier integrated in MFTJs with cobalt top electrodes. As previously reported for other MFTJs with similar electrodes, …
In ferroelectric materials, spontaneous symmetry breaking leads to a switchable electric polarization, which offers significant promise for nonvolatile memories. In particular, ferroelectric tunnel junctions (FTJs) have emerged as a new resistive switching memory which exploit polarization-dependent tunnel current across a thin ferroelectric barrier. Here we demonstrate FTJs with CMOS-compatible Zr-doped HfO$_2$ (Zr:HfO$_2$) ferroelectric barriers of just 1 nm thickness, grown by atomic layer deposition on silicon. These 1 nm Zr:HfO$_2$ tunnel junctions exhibit large polarization-driven electr…
In the quest for reliable and power-efficient memristive devices, ferroelectric tunnel junctions are being investigated as potential candidates. CMOS-compatible ferroelectric hafnium oxides are at the forefront. However, in epitaxial tunnel devices with thicknesses around ${\approx}$ 4 - 6 nm, the relatively high tunnel energy barrier produces a large resistance that challenges their implementation. Here, we show that ferroelectric and electroresistive switching can be observed in ultrathin 2 nm epitaxial Hf$_{0.5}$Zr$_{0.5}$O$_2$ (HZO) tunnel junctions in large area capacitors (${\approx} 300…
The ferroelectric material is an important platform to realize non-volatile memories. So far, existing ferroelectric memory devices utilize out-of-plane polarization in ferroelectric thin films. In this paper, we propose a new type of random-access memory (RAM) based on ferroelectric thin films with the in-plane polarization called "in-plane ferroelectric tunnel junction". Apart from non-volatility, lower power usage and faster writing operation compared with traditional dynamic RAMs, our proposal has the advantage of faster reading operation and non-destructive reading process, thus overcomes…
Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric switching. In this …
Ferroelectric tunnel junctions (FTJ) based on hafnium zirconium oxide (Hf1-xZrxO2; HZO) are a promising candidate for future applications, such as low-power memories and neuromorphic computing. The tunneling electroresistance (TER) is tunable through the polarization state of the HZO film. To circumvent the challenge of fabricating thin ferroelectric HZO layers in the tunneling range of 1-3 nm range, ferroelectric/dielectric double layer sandwiched between two symmetric metal electrodes are used. Due to the decoupling of the ferroelectric polarization storage layer and a dielectric tunneling l…
The Discovery of giant tunnel electroresistance (TER) in Ferroelectric Tunnel Junction (FTJ) paves a futuristic possibility of utilizing the FTJ as a bistable resistive device with an enormously high ON/OFF ratio. In the last 20 years, numerous studies have reported that the formation of multidomain in ferroelectric material is an inevitable process to minimize the total system energy. Recent studies based on phase-field simulations have demonstrated that domain nucleation/motion substantially alters the electrostatics of a ferroelectric material. However, the impact of domain dynamics on quan…
Intimate integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrently with enhanced energy efficiency in big-data applications such as artificial intelligence. Despite decades of efforts, reliable, compact, energy efficient and scalable memory devices are elusive. Ferroelectric Field Effect Transistors (FE-FETs) are a promising candidate but their scalability and performance in a back-end-of-line (BEOL) process remain unattained. Here, we present scalable BEOL compatible FE-FETs …
This paper introduces the first tunable ferroelectric capacitor (FeCAP) based unreleased RF MEMS resonator, integrated seamlessly in Texas Instruments' 130nm Ferroelectric RAM (FeRAM) technology. An array of FeCAPs in this complementary metal-oxide-semiconductor (CMOS) technology's back-end-of-line (BEOL) process were used to define the acoustic resonance cavity as well as the electromechanical transducers. To achieve high quality factor (Q) of the resonator, acoustic waveguiding for vertical confinement within the CMOS stack is studied and optimized. Additional design considerations are discu…
We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.
Designing high endurance Hf0.5Zr0.5O2 capacitors through engineered recovery from fatigue for non-volatile ferroelectric memory and neuromorphic hardware
In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ωmm and a low contact resistivity of 1.1{\times}10-7 Ωcm2. The ITO transistor with a recessed channel and …
Breakdown and polarization contrasts in ferroelectric devices observed by operando laser-based photoemission electron microscopy with the AC/DC electrical characterization system
Numerous neural network circuits and architectures are presently under active research for application to artificial intelligence and machine learning. Their physical performance metrics (area, time, energy) are estimated. Various types of neural networks (artificial, cellular, spiking, and oscillator) are implemented with multiple CMOS and beyond-CMOS (spintronic, ferroelectric, resistive memory) devices. A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across several application cases. Promising architecture/device combinations are …
The current work reports an efficient deep neural network (DNN) accelerator where synaptic weight elements are controlled by ferroelectric domain dynamics. An integrated device-to-algorithm framework for benchmarking novel synaptic devices is used. In P(VDF-TrFE) based ferroelectric tunnel junctions, analog conductance states are measured using a custom pulsing protocol and associated custom circuits and array architectures for DNN training is simulated. Our results show precise control of polarization switching dynamics in multi-domain, polycrystalline ferroelectric thin films can produce con…
The multiple ferroelectric polarization tuned by external electric field could be used to simulate the biological synaptic weight. Ferroelectric synaptic devices have two advantages compared with other reported ones: One is the intrinsic switching of ferroelectric domains without invoking of defect migration as in resistive oxides contributes reliable performance in these ferroelectric synapses. Another tremendous advantage is the extremely low energy consumption because the ferroelectric polarization is manipulated by electric field which eliminate the Joule heating by current as in magnetic …
Superparamagnetic tunnel junctions (SMTJs) have emerged as a competitive, realistic nanotechnology to support novel forms of stochastic computation in CMOS-compatible platforms. One of their applications is to generate random bitstreams suitable for use in stochastic computing implementations. We describe a method for digitally programmable bitstream generation based on pre-charge sense amplifiers. This generator is significantly more energy efficient than SMTJ-based bitstream generators that tune probabilities with spin currents and a factor of two more efficient than related CMOS-based imple…
We perform the characterization and modeling of a floating-gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hotelectron injection. These two injection mechanisms are characterized and modeled in compact equations both at 300 K and 15 K. At c…
