Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf$_{57}$Zr$_{43}$O$_{2}$ (HZO) field effect transistor (FeFET) with good linearity. Our FeFET operates with a low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been done over 4-bits depth with low noise (1%) in the tungsten oxide (WO$_{x}$) read out channel. By adjusting the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET can be engineered from 1% to 200% with an on-resistance ideally >100 kOhm, depending on the channel geometry. The device concept is using earth-abundant materials, and is compatible with a back end of line (BEOL) integration into complementary metal-oxidesemiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high density, large-scale integrated arrays of artificial analog synapses.
Neuromorphic Computing (NC), which emulates neural activities of the human brain, is considered for low-power implementation of artificial intelligence. Towards realizing NC, fabrication, and investigations of hardware elements such as synaptic devices and neurons are essential. Electrolyte gating has been widely used for conductance modulation by massive carrier injections and has proven to be an effective way of emulating biological synapses. Synaptic devices, in the form of synaptic transistors, have been studied using a wide variety of materials. However, studies on metallic channel based …
Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classic…
Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. We provide experimental measurements of the synaptic characteristics for a $28nm$ high-k metal gate technology based device and develop an experimentally calibrated device model for large-scale system performan…
Learning and logic are fundamental brain functions that make the individual to adapt to the environment, and such functions are established in human brain by modulating ionic fluxes in synapses. Nanoscale ionic/electronic devices with inherent synaptic functions are considered to be essential building blocks for artificial neural networks. Here, Multi-terminal IZO-based artificial synaptic transistors gated by fast proton-conducting phosphosilicate electrolytes are fabricated on glass substrates. Proton in the SiO2 electrolyte and IZO channel conductance are regarded as the neurotransmitter an…
In this letter, we present an original demonstration of an associative learning neural network inspired by the famous Pavlov's dogs experiment. A single nanoparticle organic memory field effect transistor (NOMFET) is used to implement each synapse. We show how the physical properties of this dynamic memristive device can be used to perform low power write operations for the learning and implement short-term association using temporal coding and spike timing dependent plasticity based learning. An electronic circuit was built to validate the proposed learning scheme with packaged devices, with …
Brain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current computing paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due to their ability to natively perform in-memory computing and fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need to be compatible with fabrication processes and materials of industrial CMOS technologies. Herein, we report a compl…
Neuromorphic computing based on spiking neural networks has the potential to significantly improve on-line learning capabilities and energy efficiency of artificial intelligence, specially for edge computing. Recent progress in computational neuroscience have demonstrated the importance of heterosynaptic plasticity for network activity regulation and memorization. Implementing heterosynaptic plasticity in hardware is thus highly desirable, but important materials and engineering challenges remain, calling for breakthroughs in neuromorphic devices. In this mini-review, we propose an overview of…
This paper proposes four quadrant analog multiplier using CMOS-memristor circuit. Currently, there are plenty of analog multipliers using resistors and CMOS transistors. They can attain perfect multiplication but have several disadvantages such as lower processing speed, higher power consumption and larger chip areas. Memristor based circuits are introduced to resolve the mentioned drawbacks. In this paper current mode four quadrant multiplier based on squaring circuits is taken as a framework, and CMOS transistors are replaced with memristors. The circuit design is simulated with SPICE, and v…
In this work, we experimentally demonstrate two key building blocks for realizing Binary/Ternary Neural Networks (BNNs/TNNs): (i) 130 nm CMOS based sigmoidal neurons and (ii) HfOx based multi-level (MLC) OxRAM-synaptic blocks. An optimized vector matrix multiplication programming scheme that utilizes the two building blocks is also presented. Compared to prior approaches that utilize differential synaptic structures, a single device per synapse with two sets of READ operations is used. Proposed hardware mapping strategy shows performance change of <5% (decrease of 2-5% for TNN, increase of 0.2…
University of California, Los Angeles（加州大学洛杉矶分校）；University of California, Irvine（加州大学欧文分校）；National Chiao Tung University（国立交通大学）；Kneron, Inc（Kneron公司）
An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. Through implementing the sequential analog fabric (SAF), the engine mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 7…
Despite huge success of artificial intelligence, hardware systems running these algorithms consume orders of magnitude higher energy compared to the human brain, mainly due to heavy data movements between the memory unit and the computation cores. Spiking neural networks (SNNs) built using bio-plausible neuron and synaptic models have emerged as the power-efficient choice for designing cognitive applications. These algorithms involve several lookup-table (LUT) based function evaluations such as high-order polynomials and transcendental functions for solving complex neuro-synaptic models, that …
We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.
CMOS-transistors circuits have been used as a conventional approach for designing an analog multiplier in modern era of industrial electronics. However, previous studies have shown, that based on the working region of transistors, such as saturation or weak inversion regions, the circuit may face issues with output ranges and accuracy. One possible solution to that problem could be choosing CMOS-memristors as a basis for the circuit. Although memristor research is still a growing and promising field, one could argue that its implementation could bring many benefits such as increased circuit de…
Traditional computation based on von Neumann architecture is limited by the time and energy consumption due to data transfer between the storage and the processing units. The von Neumann architecture is also inefficient in solving unstructured, probabilistic, and real-time problems. To address these challenges, a new brain-inspired neuromorphic computational architecture is required. Due to absence of resistance-capacitance (RC) delay, high bandwidth and low power consumption, optoelectronic artificial synaptic devices are highly attractive. Yet stable, scalable, and complementary-metal-oxide-…
Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work we leverage the stochastic switching of a three-state ferroelectric field effect transistor (FeFET) to implement a long-term and short-term 2-tier stochastic synaptic memory with a single device. Experimental measurements are performed on a scal…
Non-Boolean computing based on emerging post-CMOS technologies can potentially pave the way for low-power neural computing platforms. However, existing work on such emerging neuromorphic architectures have either focused on solely mimicking the neuron, or the synapse functionality. While memristive devices have been proposed to emulate biological synapses, spintronic devices have proved to be efficient at performing the thresholding operation of the neuron at ultra-low currents. In this work, we propose an All-Spin Artificial Neural Network where a single spintronic device acts as the basic bu…
Beyond conventional organic thin-film transistors, this thesis explores possible paths for the fourth wave of organic electronics. In this context, mixed ionic-electronic conductors and organic electro-chemical transistors (OECTs) are identified as highly promising approaches for electronic bio-interfaces enabling ultra-sensitive detection of biological signals. Furthermore, these systems show fundamental properties of biological synapses, namely the synaptic plasticity, which renders the possibility to build brain-inspired, neuromorphic networks enabling highly efficient computing. In particu…
Nazarbayev University（纳扎尔巴耶夫大学）；King Abdullah University of Science and Technology（阿卜杜拉国王科技大学）
Synaptic Sampling Machine (SSM) is a type of neural network model that considers biological unreliability of the synapses. We propose the circuit design of the SSM neural network which is realized through the memristive-CMOS crossbar structure with the synaptic sampling cell (SSC) being used as a basic stochastic unit. The increase in the edge computing devices in the Internet of things era, drives the need for hardware acceleration for data processing and computing. The computational considerations of the processing speed and possibility for the real-time realization pushes the synaptic sampl…
Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the mil- lisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a ne…
As one of the most important members of the two dimensional chalcogenide family, molybdenum disulphide (MoS2) has played a fundamental role in the advancement of low dimensional electronic, optoelectronic and piezoelectric designs. Here, we demonstrate a new approach to solid state synaptic transistors using two dimensional MoS2 floating gate memories. By using an extended floating gate architecture which allows the device to be operated at near-ideal subthreshold swing of 77 mV/decade over four decades of drain current, we have realised a charge tunneling based synaptic memory with performanc…
The technological exploitation of ferroelectricity in CMOS electron devices offers new design opportunities, but also significant challenges from an integration, optimization and modelling perspective. We here revisit the working principle and the modelling of some novel ferroelectric based devices, with an emphasis on energy efficiency and on applications to new computational paradigms.
CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning
University of California Santa Barbara（加州大学圣巴巴拉分校）；Tohoku University（东北大学）；Research Institute of Electrical Communication, Tohoku University（东北大学电气通信研究所）；Graduate School of Engineering, Tohoku University（东北大学工学研究科）
Energy conservative devices are the need of the modern technology which leads to the development of reversible logic. The synthesis of reversible logic has become an intensely studied area as it overcomes the problem of power dissipation associated with irreversibility. Storage device such as Read-Only-Memory (ROM) can be realized in a reversible way with low power dissipation. The reversibility of ROM has not been yet realized in literature and hence, this paper presents a novel reversible ROM with its Complementary Metal Oxide Semiconductor (CMOS) realization. On the way to present the archi…
To continue scaling beyond 2-D CMOS with 3-D integration, any new 3-D IC technology has to be comparable or better than 2-D CMOS in terms of scalability, enhanced functionality, density, power, performance, cost, and reliability. Transistor-level 3-D integration carries the most potential in this regard. Recently, we proposed a stacked horizontal nanowire based transistor-level 3-D integration approach, called SN3D [1][2] that solves scaling challenges and achieves tremendous benefits with respect to 2-D CMOS while keeping manageable thermal profile. In this paper, we present the cost analysis…
Phase change memory (PCM) is an emerging high speed, high density, high endurance, and scalable non-volatile memory technology which utilizes the large resistivity contrast between the amorphous and crystalline phases of chalcogenide materials such as Ge2Sb2Te5 (GST). In addition to being used as a standalone memory, there has been a growing interest in integration of PCM devices on top of the CMOS layer for computation in memory and neuromorphic computing. The large CMOS overhead for memory controllers is a limiting factor for this purpose. Transferring functionality like routing, multiplexin…
Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the key requirement of online learning in order to adapt and learn new features in uncontrolled environments. However, embedding online learning in SNNs is currently hindered by high incurred complexity and area overheads. In this work, we present ODIN, a…
Present day computers expend orders of magnitude more computational resources to perform various cognitive and perception related tasks that humans routinely perform everyday. This has recently resulted in a seismic shift in the field of computation where research efforts are being directed to develop a neurocomputer that attempts to mimic the human brain by nanoelectronic components and thereby harness its efficiency in recognition problems. Bridging the gap between neuroscience and nanoelectronics, this paper attempts to provide a review of the recent developments in the field of spintronic …
Modern computing systems based on the von Neumann architecture are built from silicon complementary metal oxide semiconductor (CMOS) transistors that need to operate under practically error free conditions with 1 error in $10^{15}$ switching events. The physical dimensions of CMOS transistors have scaled down over the past five decades leading to exponential increases in functional density and energy consumption. Today, the energy and delay reductions from scaling have stagnated, motivating the search for a CMOS replacement. Of these, spintronics offers a path for enhancing the functional dens…
Generating an exponential decay function with a time constant on the order of hundreds of milliseconds is a mainstay for neuromorphic circuits. Usually, either subthreshold circuits or RC-decays based on transconductance amplifiers are used. In the latter case, transconductances in the 10 pS range are needed. However, state-of-the-art low-transconductance amplifiers still require too much circuit area to be applicable in neuromorphic circuits where >100 of these time constant circuits may be required on a single chip. We present a silicon verified operational transconductance amplifier that ac…
Dedicated hardware implementations of spiking neural networks that combine the advantages of mixed-signal neuromorphic circuits with those of emerging memory technologies have the potential of enabling ultra-low power pervasive sensory processing. To endow these systems with additional flexibility and the ability to learn to solve specific tasks, it is important to develop appropriate on-chip learning mechanisms.Recently, a new class of three-factor spike-based learning rules have been proposed that can solve the temporal credit assignment problem and approximate the error back-propagation alg…
Despite all the progress of semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. One of the most prospective candidates to provide comparable complexity, while operating much faster and with manageable power dissipation, are so-called CrossNets based on hybrid CMOS/memristor circuits. In these circuits, the usual CMOS stack is augmented with one or several crossbar layers, with adjustable two-terminal memristors at each crosspoint…
Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradient-descent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multi-layer SNNs with memristive neuromorphic hardware showing a small loss in the performance compared wit…
Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to conventional CMOS FETs. Previous theoretical and experimental works [1][2] on JNFETs have considered polysilicon gates and silicon-dioxide dielectric. However, with further scaling, JNFETs will suffer from deleterious effects of doped polysilicon such as high resistance, additional capacitance due to gate-oxide interface depletion, and incompatibility with hi…
