发表机构
Forschungszentrum Jülich GmbH; RWTH Aachen University（于利希研究中心; 亚琛工业大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
提出28nm CMOS与TaOx RRAM集成的2T1R架构，通过并联LD/HD晶体管实现可靠存内计算，支持多级电导调谐及aCAM设计，并在15x15阵列上验证了MAC操作。
AI 中文摘要
这项工作提出了OTTER，一个与基于TaOx的价态变化机制（VCM）RRAM共同集成的28纳米CMOS平台，展示了一种用于可靠存内计算的双晶体管-单忆阻器件（2T1R）架构。2T1R单元将低驱动电流（LD）晶体管和高驱动电流（HD）晶体管并联组合，分别为SET编程和RESET操作提供专用偏置路径。通过使用物理紧凑模型JART VCM Rth对多种晶体管配对配置进行系统的实验和模拟比较，得出了晶体管尺寸设计指南，建立了完全RESET所需的最小RESET晶体管W/L与SET电流限制之间的函数关系。2T1R单元在基于脉冲的编程下进一步表征，展示了在六个可编程电平上具有窄且分离良好的电导状态的模拟多级电导调谐。基于相同2T1R单元的模拟内容寻址存储器（aCAM）设计还在电路级别进行了分析，评估了顶部和底部连接RRAM比较器配置之间的权衡。此外，在15 x 15 2T1R交叉阵列上演示了存内计算（CIM）乘加（MAC）操作的硬件实现。
英文摘要
This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.
