High electron mobility transistors are widely used as microwave amplifiers owing to their low microwave noise figure. Electronic noise in these devices is typically modeled by noise sources at the gate and drain. While consensus exists regarding the origin of the gate noise, that of drain noise is a topic of debate. Here, we report a theory of drain noise as a type of partition noise arising from real-space transfer of hot electrons from the channel to the barrier. The theory accounts for the magnitude and dependencies of the drain temperature and suggests strategies to realize devices with lower noise figure.
A "spin-flip transistor" is a lateral spin valve consisting of ferromagnetic source drain contacts to a thin-film normal-metal island with an electrically floating ferromagnetic base contact on top. We analyze the \emph{dc}-current-driven magnetization dynamics of spin-flip transistors in which the source-drain contacts are magnetized perpendicularly to the device plane by magnetoelectronic circuit theory and the macrospin Landau-Lifshitz-Gilbert equation. Spin flip scattering and spin pumping effects are taken into account. We find a steady-state rotation of the base magnetization at GHz freq…
While decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an exponential increase in Off-current with drain voltage, due to modulation of the Schottky barriers at both the source and drain contact. We illustrate this with results for bottom-gated ambipolar CNFETs with oxides of 2 and 5 nm, and give an explicit scaling rule for the drain voltage. Above the drain voltage limit, the Off-current becomes large and has equal ele…
Most carbon nanotube field-effect transistors (CNTFETs) directly attach metal source/drain contacts to an intrinsic nanotube channel. When the gate oxide thickness is reduced, such transistors display strong ambipolar conduction, even when the Schottky barrier for electrons (or for holes) is zero. The resulting leakage current, which increases exponentially with the drain voltage, constrains the potential applications of such devices. In this paper, we use numerical simulations to show that if CNT based metal-oxide-semiconductor (MOS) FETs can be achieved by using heavily doped CNT sections as…
In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S<60 mV/decade). In this letter, a comprehensive physics-based surface potential and drain current model for the negative capacitance field-effect transistor is reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. Moreover it provides a model core…
We have demonstrated that depletion/enhancement-mode b-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped b-Ga2O3 nano-membrane as the channel. b-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the loca…
We report a strategy to design nanoscale cold-source field-effect transistors (CS-FETs) with bias-independent sub-60 mV/dec subthreshold swing (SS). By first-principles calculations and quantum-transport simulations, we reveal that the energy alignment of density of states (DOS) between the drain and source electrodes is critical to achieving bias-independent SS. By defining "gate window", we propose a device model to demonstrate how similar slopes of the drain DOS falling into the gate window can stabilize the SS under different bias. This study underscores the significance of drain DOS engin…
I present a compact physics-based model of the drain current, charge and capacitance of graphene field-effect transistors, of relevance for exploration of DC, AC and transient behavior of graphene based circuits. The physical framework is a field-effect model and drift-diffusion carrier transport incorporating saturation velocity effects. First, an explicit model has been derived for the drain current. Using it as a basis, explicit closed-form expressions for the charge and capacitances based on the Ward-Dutton partition scheme, covering continuosly all operation regions. The model is of speci…
In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semicondu…
In this article, we present a configurable field-effect transistor (FET), where not only polarity (n- and p-type), but the conduction mechanism of a FET can also be configured dynamically. As a result, we can have both types of devices, high-performance MOSFET and low-power TFET, for computational and power efficient system on chip (SoC) products. The calibrated 3D-TCAD simulation results validate characteristics and functionalities of the configurable FET, and showed good consistency with the static conventional MOSFET (or TFET).
We present a compact physics-based model of the current-voltage characteristics of graphene field-effect transistors, of especial interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed. The physical framework is a field-effect model and drift-diffusion carrier transport. Explicit closed-form expressions have been derived for the drain current covering continuosly all operation regions. The model has been benchmarked with measured prototype devices, demonstrating accuracy and predictive behavior. Finally, we show an example of projection o…
A simple model based on the WKB approximation for one-dimensional ballistic multi--gate reconfigurable field--effect transistors (RFETs) with Schottky-Barrier contacts has been developed for the drain current taking into account electron and hole band-to-band tunneling. By using a proper approximation of both the Fermi-Dirac distribution function and transmission probability, an analytical solution for the Landauer integral can be obtained. A comparative analysis of the two-gate and triple-gate RFETs is performed based on the numerical integration of the current integral.
We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si/SiO$_2$ substrates have high carrier mobilities of up to 6,300 cm$^2$/Vs. Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio fre…
Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.
We report on a new computational model to efficiently simulate carbon nanotubebased field effect transistors (CNT-FET). In the model, a central region is formed by a semiconducting nanotube that acts as the conducting channel, surrounded by a thin oxide layer and a metal gate electrode. At both ends of the semiconducting channel, two semi-infinite metallic reservoirs act as source and drain contacts. The current-voltage characteristics are computed using the Landauer formalism, including the effect of the Schottky barrier physics. The main operational regimes of the CNT-FET are described, incl…
In this letter, we report on high performance depletion/enhancement (D/E)-mode beta-Ga2O3 on insulator (GOOI) field-effect transistors (FETs) with record high drain currents (ID) of 600/450 mA/mm, which are nearly one order of magnitude higher than any other reported ID values. The threshold voltage (VT) can be modulated by varying the thickness of the beta-Ga2O3 films and the E-mode GOOI FET can be simply achieved by shrinking the beta-Ga2O3 film thickness. Benefiting from the good interface between beta-Ga2O3 and SiO2 and wide bandgap of beta-Ga2O3, a negligible transfer characteristic hyste…
Spin-based metal-oxide-semiconductor field-effect transistors (MOSFET) with a high-mobility III-V channel are studied using self-consistent quantum corrected ensemble Monte Carlo device simulations of charge and spin transport. The simulations including spin-orbit coupling mechanisms (Dresselhaus and Rashba coupling) examine the electron spin transport in the 25 nm gate length In$_{0.7}$Ga$_{0.3}$As MOSFET. The transistor lateral dimensions (the gate length, the source-to-gate, and the gate-to-drain spacers) are increased to investigate the spin-dependent drain current modulation induced by th…
We have fabricated and measured ballistic graphene transistors with two oblique gates that can be independently biased. The gate lengths are about 38 nm and are separated by a distance of 30 nm, the tilting angle being of 45o with respect to source and drain electrodes distanced at 190 nm. Electric measurements reveal specific properties of ballistic carrier transport, i.e. nonlinear drain voltage-drain current dependence, showing a saturation region, and negative differential resistance at certain bias voltages, which cannot be explained without physical mechanisms related to ballistic transp…
High performance enhancement mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal-tube contacts, high dielectric constant HfO2 films as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes. The combination of these elements affords high ON currents, subthreshold swings of ~ 70-80 mV/decade, and allows for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles that of MOSFETs and can impart excellent OFF states to nanotube FETs under aggressive vertical scali…
In this manuscript, we present a field effect transistor with a channel consisting of a two-dimensional electron gas located at the interface between an ultrathin metallic film of Ni and a p-type Si(111) substrate. We have demonstrated that the two-dimensional electron gas channel is modulated by the gate voltage. The dependence of the drain current on the drain voltage has no saturation region, similar to a field effect transistor based on graphene. However, the transport in this transistor is not ambipolar, as in graphene, but unipolar.
Spin-based logic devices could operate at very high speed with very low energy consumption and hold significant promise for quantum information processing and metrology. Here, an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with a Bloch equation model using a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings is developed and applied to a spin field effect transistor (spinFET) operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a \SI{25}{nm}…
In this article, we study the properties of metal contacts to single-layer molybdenum disulfide (MoS2) crystals, revealing the nature of switching mechanism in MoS2 transistors. On investigating transistor behavior as contact length changes, we find that the contact resistivity for metal/MoS2 junctions is defined by contact area instead of contact width. The minimum gate dependent transfer length is ~0.63 μm in the on-state for metal (Ti) contacted single-layer MoS2. These results reveal that MoS2 transistors are Schottky barrier transistors, where the on/off states are switched by the tuning …
We propose three-terminal spin devices with graphene nanoribbons (terminals) and a graphene flake (channel) to generate a highly spin-polarized current without an external magnetic field or ferromagnetic electrodes. The Hubbard repulsion within the mean-field approximation plays the main role to separate the unpolarized electric current at the source terminal into spin-polarized currents at the drain terminals. It is shown that by modulating one of the drain voltages, a fully spin-polarized current can be generated in the other drain terminal. In addition, the geometry of the channel and the a…
We present an analytical device model for a field-effect transistor based on a heterostructure which consists of an array of nanoribbons clad between the highly conducting substrate (the back gate) and the top gate controlling the source-drain current. The equations of the model of a graphene nanoribbon field-effect transistor (GNR-FET) include the Poisson equation in the weak nonlocality approximation. Using this model, we find explicit analytical formulas for the spatial distributions of the electric potential along the channel and for the GNR-FET current-voltage characteristics (the depende…
We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative outpu…
High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analog applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A record high transconductance of 4 S/mm is also achieved among all transistors with a planar stru…
In this paper, we report a novel chemical doping technique to reduce the contact resistance (Rc) of transition metal dichalcogenides (TMDs) - eliminating two major roadblocks (namely, doping and high Rc) towards demonstration of high-performance TMDs field-effect transistors (FETs). By using 1,2 dichloroethane (DCE) as the doping reagent, we demonstrate an active n-type doping density > 2*1019 cm-3 in a few-layer MoS2 film. This enabled us to reduce the Rc value to a record low number of 0.5 kohm*um, which is ~10x lower than the control sample without doping. The corresponding specific contact…
A physics-based model for the surface potential and drain current for monolayer transition metal dichalcogenide (TMD) field-effect transistor (FET) is presented. Taking into account the 2D density-of-states of the atomic layer thick TMD and its impact on the quantum capacitance, a model for the surface potential is presented. Next, considering a drift-diffusion mechanism for the carrier transport along the monolayer TMD, an explicit expression for the drain current has been derived. The model has been benchmarked with a measured prototype transistor. Based on the proposed model, the device des…
We study gated field effect transistors (FETs) with fractal geometries under Dyakonov and Shur asymmetric boundary conditions, where the source and drain span the left and right edges of the device respectively. An AC THz potential difference is applied between source and gate while a static source-drain voltage, rectified by the nonlinearities of FET electrons, is measured. We find, for a recursion depth, n, that resonant peaks in the potential integrated along the drain at $ω_n = 3nω_0$ are amplified while all other are diminished. Additionally, we find the presence of peaks with frequencies…
We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two…
We present temperature dependent $I-V$ measurements of short channel MoS$_2$ field effect devices at high source-drain bias. We find that although the $I-V$ characteristics are Ohmic at low bias, the conduction becomes space charge limited at high $V_{DS}$ and existence of an exponential distribution of trap states was observed. The temperature independent critical drain-source voltage ($V_c$) was also determined. The density of trap states was quantitatively calculated from $V_c$. The possible origin of exponential trap distribution in these devices is also discussed.
This work reports the design and analysis of an n-type tunneling field effect transistor based on InN. The tunneling current is evaluated from the fundamental principles of quantum mechanical tunneling and semiclassical carrier transport. We investigate the RF performance of the device. High transconductance of 2 mS/um and current gain cut-off frequency of around 460 GHz makes the device suitable for THz applications. A significant reduction in gate to drain capacitance is observed under relatively higher drain bias. In this regard, the avalanche breakdown phenomenon in highly doped InN juncti…
By generalizing the classical linear response theory of stick percolation to nonlinear regime, we find that the drain current of a Nanobundle Thin Film Transistor (NB-TFT) is described under a rather general set of conditions by a universal scaling formula ID = A/LS g(LS/LC, rho_S * LS * LS) f(VG, VD), where A is a technology-specific constant, g is function of geometrical factors like stick length (LS), channel length (LC), and stick density (rho_S) and f is a function of drain (VD) and gate (VG) biasing conditions. This scaling formula implies that the measurement of full I-V characteristics…
We demonstrate a tunable negative differential resistance controlled by spin blockade in single electron transistors. The single electron transistors containing a few electrons and spin polarized source and drain contacts were formed in GaAs/GaAlAs heterojunctions using metallic gates. Coulomb blockade measurements performed as a function of applied source-drain bias, electron number and magnetic field reveal well defined regimes where a decrease in the current is observed with increasing bias. We establish that the origin of the negative differential regime is the spin-polarized detection of …
We report on an unconventional $macroscopic$ field effect transistor composed of electrons floating above the surface of superfluid helium. With this device unique transport regimes are realized in which the charge density of the electron layer can be controlled in a manner not possible in other material systems. In particular, we are able to manipulate the collective behavior of the electrons to produce a highly non-uniform, but precisely controlled, charge density to reveal a negative source-drain current. This behavior can be understood by considering the propagation of damped charge oscill…
The current driven magnetization dynamics of a thin-film, three magnetic terminal device (spin-flip transistor) is investigated theoretically. We consider a magnetization configuration in which all magnetizations are in the device plane, with source-drain magnetizations chosen fixed and antiparallel, whereas the third contact magnetization is allowed to move in a weak anisotropy field that guarantees thermal stability of the equilibrium structure at room temperature. We analyze the magnetization dynamics of the free layer under a dc source-drain bias current within the macrospin model and magn…
We show simultaneous p and n type carrier injection in bilayer graphene channel by varying the longitudinal bias across the channel and the top gate voltage. The top gate is applied electrochemically using solid polymer electrolyte and the gate capacitance is measured to be 1.5 $μF/cm^2$, a value about 125 times higher than the conventional SiO$_2$ back gate capacitance. Unlike the single layer graphene, the drain-source current does not saturate on varying the drain-source bias voltage. The energy gap opened between the valence and conduction bands using top and back gate geometry is estimate…
We performed a comprehensive scaling study of Schottky barrier carbon nanotube transistors using self-consistent, atomistic scale simulations. We restrict our attention to Schottky barrier carbon nanotube FETs whose metal source/drain is attached to an intrinsic carbon nanotube channel. Ambipolar conduction is found to be an important factor that must be carefully considered in device design, especially when the gate oxide is thin. The channel length scaling limit imposed by source-drain tunneling is found to be between 5nm and 10nm, depending on the off-current specification. Using a large di…
We measure hole transport in poly(3-hexylthiophene) field effect transistors with channel lengths from 3 $μ$m down to 200 nm, from room temperature down to 10 K. Near room temperature effective mobilities inferred from linear regime transconductance are strongly dependent on temperature, gate voltage, and source-drain voltage. As $T$ is reduced below 200 K and at high source-drain bias, we find transport becomes highly nonlinear and is very strongly modulated by the gate. We consider whether this nonlinear transport is contact limited or a bulk process by examining the length dependence of lin…
We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions are realized by low energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the nanowire resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and ON/O…
We demonstrate a tunnel field effect transistor based on a lateral heterostructure patterned from an $\mathrm{LaAlO_3/SrTiO_3}$ electron gas. Charge is injected by tunneling from the $\mathrm{LaAlO_3}$/$\mathrm{SrTiO_3}$ contacts and the current through a narrow channel of insulating $\mathrm{SrTiO_3}$ is controlled via an electrostatic side gate. Drain-source I/V-curves have been measured at low and elevated temperatures. The transistor shows strong electric-field and temperature-dependent behaviour with a steep sub-threshold slope %of up to as small as $10\:\mathrm{mV/decade}$ and a transcon…
In this study, a model of a Schottky-barrier carbon nanotube field- effect transistor (CNT-FET), with ferromagnetic contacts, has been developed. The emphasis is put on analysis of current-voltage characteristics as well as shot (and thermal) noise. The method is based on the tight-binding model and the non- equilibrium Green's function technique. The calculations show that, at room temperature, the shot noise of the CNT FET is Poissonian in the sub-threshold region, whereas in elevated gate and drain/source voltage regions the Fano factor gets strongly reduced. Moreover, transport properties …
Negative differential resistance (NDR) with room temperature peak-valley-ratio of 8 has been observed in a ballistic field-effect-transistor (FET) based on graphene, having an oblique top gate. Graphene FETs with a top gate inclination angle of 45 degrees and a drain-source distance of 400 nm were fabricated on a chip cut from a 4 inch graphene wafer grown by CVD. From the 60 measured devices, NDR was observed only in the regions where the CVD graphene displays the Raman signature of defectless monolayers. In other specific positions on the wafer, where graphene quality was not high enough and…
In our previous paper, we reported on switchable monolayer MoS2 transistors with a high on-off ratio and we claim that dielectric screening can be used to increase the mobility of monolayer MoS2. We estimated its mobility using a method previously applied by Lemme et al. to top-gated graphene nanoribbons. We discuss here the comments raised by M. Fuhrer and J. Hone in their post 1301.4288 and give our own estimates of the possible errors in previous mobility measurements and their origins.
Tens of graphene transistors with nanoperforated channels and different channel lengths were fabricated at the wafer scale. The nanoholes have a central diameter of 20 nm and a period of 100 nm, the lengths of the channel being of 1, 2, 4 or 8 micrometers. We have found that the mobility in these 2 micrometer-wide transistors varies from about 10400 cm2/Vs for a channel length of 1 micrometer to about 550 cm2/Vs for a channel length of 8 micrometer. Irrespective of the mobility value, in all transistors the on-off ratio is in the range 10^3-10^4 at drain and gate voltages less than 2 V. The ch…
We utilize an organic polymer buffer layer between graphene and conventional gate dielectrics in top-gated graphene transistors. Unlike other insulators, this dielectric stack does not significantly degrade carrier mobility, allowing for high field-effect mobilities to be retained in top-gate operation. This is demonstrated in both two-point and four-point analysis, and in the high-frequency operation of a graphene transistor. Temperature dependence of the carrier mobility suggests that phonons are the dominant scatterers in these devices.
We fabricate MoS2 field effect transistors on both SiO2 and polymethyl methacrylate (PMMA) dielectrics and measure charge carrier mobility in a four-probe configuration. For multilayer MoS2 on SiO2, the mobility is 30-60 cm2/Vs, relatively independent of thickness (15-90 nm), and most devices exhibit unipolar n-type behavior. In contrast, multilayer MoS2 on PMMA shows mobility increasing with thickness, up to 470 cm2/Vs (electrons) and 480 cm2/Vs (holes) at thickness ~50 nm. The dependence of the mobility on thickness points to a long-range dielectric effect of the bulk MoS2 in increasing mobi…
A spin metal-oxide-semiconductor field-effect-transistor (spin MOSFET), which combines a Schottky-barrier MOSFET with ferromagnetic source and drain contacts, is a promising device for spintronic logic. Previous simulation studies predict that this device should display a very high magnetoresistance (MR) ratio (between the cases of parallel and anti-parallel magnetizations) for the case of half-metal ferromagnets (HMF). We use the non-equilibrium Green's function (NEGF) formalism to describe tunneling and carrier transport in this device and to incorporate spin relaxation at the HMF-semiconduc…
Using a block of three separated solid elements, a thermal source and drain together with a gate made of an insulator-metal transition material exchanging near-field thermal radiation, we introduce a nanoscale analog of a field-effect transistor which is able to control the flow of heat exchanged by evanescent thermal photons between two bodies. By changing the gate temperature around its critical value, the heat flux exchanged between the hot body (source) and the cold body (drain) can be reversibly switched, amplified, and modulated by a tiny action on the gate. Such a device could find impo…
We report on "graphene-like" mechanical exfoliation of thin films of titanium ditelluride and investigation of their electronic properties. The exfoliated crystalline TiTe2 films were used as the channel layers in the back-gated field-effect transistors fabricated with Ti/Al/Au metal contacts on SiO2/Si substrates. The room-temperature current-voltage characteristics revealed strongly non-linear behavior with signatures of the source-drain threshold voltage similar to those observed in the charge-density-wave devices. The drain-current showed an unusual non-monotonic dependence on the gate bia…
We report direct measurements of the potential barriers and electronic coupling between nanowire segments within a sketch-based oxide nanotransistor (SketchFET) device. Near room temperature, switching is governed by thermally activation across a potential barrier controlled by the nanowire gate. Below T=150 K, a crossover to quantum field emission is observed that is sensitive to structural phase transitions in the SrTiO3 layer. This direct measurement of the source-drain and gate-drain energy barriers is crucial for the development of room-temperature logic and memory elements and low-temper…
We report the first observation of gate-controlled field emission current from a tungsten diselenide (WSe2) monolayer, synthesized by chemical-vapour deposition on SiO2/Si substrate. Ni contacted WSe2 monolayer back-gated transistors, under high vacuum, exhibit n-type conduction and drain-bias dependent transfer characteristics, which are attributed to oxygen/water desorption and drain induced Schottky barrier lowering, respectively. The gate-tuned n-type conduction enables field emission, i.e. the extraction of electrons by quantum tunnelling, even from the flat part of the WSe2 monolayers. E…
Improving carrier mobilities of two-dimensional (2D) semiconductors is highly sought after. Recently, Ng. et al. [1] reported rippled molybdenum disulfide (MoS$_2$) transistors on bulged silicon nitride (SiN$_x$) substrates that exhibit high electron mobilities up to ~900 cm$^2$V$^{-1}$s$^{-1}$. The high mobility values were attributed to the suppression of electron-phonon scattering by the lattice distortion in the rippled MoS$_2$ channel. While the results are compelling, this Matters Arising shows that the mobility values in ref. [1] are likely to be overestimated due to invasive voltage pr…
We describe the fundamental trade-offs in engineering the mobility, current saturation and ON- OFF ratios in graphene transistors. Surprisingly, the trade-offs arise solely from an asymptotic constraint on the high energy bandstructure and independent of scattering processes. This places graphite derivatives (bulk monolayer graphene, uniaxially strained graphene nanoribbons, carbon nanotubes and bilayer graphene) on the same 3-parameter mobility-bandgap-scattering length (μ - Egap -λ) plot, proximal to other semiconductors. In addition to this low-bias trade-off, the high bias current bears si…
In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra thin body silicon-on-insulator MOSFETs can not compete with graphene FET values.
In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance,…
The analytical model of the small-signal current and capacitance characteristics of RF graphene FET is presented. The model is based on explicit distributions of chemical potential in graphene channels (including ambipolar conductivity at high source-drain bias) obtained in the framework of drift-diffusion current continuity equation solution. Small-signal transconductance and output conductance characteristics are modeled taking into account the two modes of drain current saturation including drift velocity saturation or electrostatic pinch-off. Analytical closed expression for the complex cu…
We have used an electro-optic technique to measure the position-dependent infrared absorption of holes injected into a thin crystal of the organic semiconductor, 6,13-bis(triisopropylsilylethynyl)-pentacene incorporated in a field-effect transistor. By applying square-wave voltages of variable frequency to the gate or drain, one can measure the time it takes for charges to accumulate on the surface, and therefore determine their mobility.
In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested usi…
