Fabrication of superconducting through-silicon vias
Justin L. Mallek, Donna-Ruth W. Yost, Danna Rosenberg, Jonilyn L. Yoder, Gregory Calusine, Matt Cook, Rabindra Das, Alexandra Day, Evan Golden, David K. Kim, Je… 展开作者
Justin L. Mallek, Donna-Ruth W. Yost, Danna Rosenberg, Jonilyn L. Yoder, Gregory Calusine, Matt Cook, Rabindra Das, Alexandra Day, Evan Golden, David K. Kim, Jeffery Knecht, Bethany M. Niedzielski, Mollie Schwartz, Arjan Sevi, Corey Stull, Wayne Woods, Andrew J. Kerman, William D. Oliver
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 $μ$m wide by 20 $μ$m long by 200 $μ$m deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
We describe a microfabrication process for superconducting through-silicon vias appropriate for use in superconducting qubit quantum processors. With a sloped-wall via geometry, we can use non-conformal metal deposition methods such as electron-beam evaporation and sputtering, which reliably deposit high quality superconducting films. Via superconductivity is validated by demonstrating zero via-to-via resistance below the critical temperature of aluminum.
We fabricate and characterize superconducting through-silicon vias and electrodes suitable for superconducting quantum processors. We measure internal quality factors of a million for test resonators excited at single-photon levels, on chips with superconducting vias used to stitch ground planes on the front and back sides of the chips. This resonator performance is on par with the state of the art for silicon-based planar solutions, despite the presence of vias. Via stitching of ground planes is an important enabling technology for increasing the physical size of quantum processor chips, and …
As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays -- provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconductin…
Nanofabrication techniques for superconducting qubits rely on resist-based masks patterned by electron-beam or optical lithography. We have developed an alternative nanofabrication technique based on free-standing silicon shadow masks fabricated from silicon-on-insulator wafers. These silicon shadow masks not only eliminate organic residues associated with resist-based lithography, but also provide a pathway to better understand and control surface-dielectric losses in superconducting qubits by decoupling mask fabrication from substrate preparation. We have successfully fabricated aluminum 3D …
In this work, we present a method for targeted, maskless, and scalable fabrication of single silicon vacancy (VSi) defect arrays in silicon carbide (SiC) using focused ion beam. The resolution of implanted VSi defects is limited to a few tens of nanometers, defined by the diameter of the ion beam. Firstly, we studied the photoluminescence (PL) spectrum and optically detected magnetic resonance (ODMR) of the generated defect spin ensemble, confirming that the synthesized centers were in the desired defect state. Then we investigated the fluorescence properties of single VSi defects and our meas…
We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection, and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum, and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in …
We present the fabrication and characterization of transmon qubits formed from aluminum Josephson junctions on two different silicon-based substrates: (i) high-resistivity silicon (Si) and (ii) silicon-on-insulator (SOI). Key to the qubit fabrication process is the use of an anhydrous hydrofluoric vapor process which removes silicon surface oxides without attacking aluminum, and in the case of SOI substrates, selectively removes the lossy buried oxide underneath the qubit region. For qubits with a transition frequency of approximately $5$GHz we find qubit lifetimes and coherence times comparab…
As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubi…
A merged-element transmon (MET) device, based on silicon (Si) fins, is proposed and the first steps to form such a "FinMET" are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on the parallel side-wall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rath…
Characterization of process-related interfacial dielectric loss in aluminum-on-silicon by resonator microwave measurements, materials analysis, and imaging
In view of the integration of membrane resonators with more complex MEMS structures, we developed a general fabrication procedure for circular shape SiN$_x$ membranes using Deep Reactive Ion Etching (DRIE). Large area and high-stress SiN$_x$ membranes were fabricated and used as optomechanical resonators in a Michelson interferometer and in a Fabry-Pérot cavity. The measurements show that the fabrication process preserves both the optical quality and the mechanical quality factor of the membrane.
Fabrication processes involving anhydrous hydrofluoric vapor etching are developed to create high-$Q$ aluminum superconducting microwave resonators on free-standing silicon membranes formed from a silicon-on-insulator wafer. Using this fabrication process, a high-impedance $8.9$GHz coil resonator is coupled capacitively with large participation ratio to a $9.7$MHz micromechanical resonator. Two-tone microwave spectroscopy and radiation pressure back-action are used to characterize the coupled system in a dilution refrigerator down to temperatures of $T_f = 11$~mK, yielding a measured electrome…
Photonic quantum technology can be enhanced by monolithic fabrication of both the underpinning quantum hardware and the corresponding electronics for classical readout and control. Together, this enables miniaturisation and mass-manufacture of small quantum devices---such as quantum communication nodes, quantum sensors and sources of randomness---and promises the precision and scale of fabrication required to assemble useful quantum computers. Here we combine CMOS compatible silicon and germanium-on-silicon nano-photonics with silicon-germanium integrated amplification electronics to improve p…
Phosphorus donor spins in silicon offer a number of promising characteristics for the implementation of robust qubits. Amongst various concepts for scale-up, the shared-control concept takes advantage of 3D scanning tunnelling microscope (STM) fabrication techniques to minimise the number of control lines, allowing the donors to be placed at the pitch limit of $\geq$30 nm, enabling dipole interactions. A fundamental challenge is to exploit the faster exchange interaction, however, the donor spacings required are typically 15 nm or less, and the exchange interaction is notoriously sensitive to …
We report an accelerated laser phase diffusion quantum entropy source with all non-laser optical and optoelectronic elements implemented in silicon photonics. The device uses efficient and robust single-laser accelerated phase diffusion methods, and implements the whole quantum entropy source scheme including an unbalanced Mach-Zehnder interferometer with optimized splitting ratio, in a 0.5 mmx1 mm footprint. We demonstrate Gbps raw entropy-generation rates in a technology compatible with conventional CMOS fabrication techniques.
