In this paper a CMOS two stage operational amplifier has been presented which operates at 1.8 V power supply at 0.18 micron (i.e., 180 nm) technology and whose input is depended on Bias Current. The op-amp provides a gain of 63dB and a bandwidth of 140 kHz for a load of 1 pF. This op-amp has a Common Mode gain of -25 dB, an output slew rate of 32 $V / μs$, and a output voltage swing. The power consumption for the op-amp is $300μW$.
This paper presents a new auto zeroing technique that combines very high-speed operation, low power consumption, and low input switching interferences. This technique has been applied to the design of CMOS flash Analog-to-Digital converter for Ultra-Wide Band applications. This project is dealt with the design of an auto zeroing amplifier with three stages. It has to be operating on 1.2 power supply voltage and the input voltage is limited to 400 mv in 130 nm CMOS technology. The CMOS auto zeroing amplifier stages are simulated in the Advanced Design System (ADS) Tool.
A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage and a 5-bit second stage, with 1-bit redundancy to relax the offset, gain, and settling requirements of the first stage. Employing the OLS technique allows for an inter-stage gain of ~4 from the dynamic residue amplifier with a settling time that is only 28% of a conventional CML amplifier. The ADC's conversion speed is further improved with the use of paral…
This paper describes a pipelined analog-to-digital converter (ADC) employing a power and area efficient architecture. The adjacent stages of a pipeline share operational amplifiers. In order to keep accuracy of the amplifiers in the first stages, they use a partially sharing technique. The feature of the proposed scheme is that it also shares the comparators. The capacitors of the first stages of a pipeline are scaled down along a pipeline for a further reducing the chip area and its power consumption. A 9-bit 20-MSamples/s ADC, intended for use in multi-channel mixed-signal chips, has been fa…
This paper presents the design and post-layout characteristics of a differential capacitance based inertial accelerometer This includes a MEMS based mechanical sensing element and a CMOS charge amplifier, which is the first stage of a readout circuit. The mechanical sensor is designed according to the SOIMUMPs fabrication process technology, and the readout circuit targeted AMS 0.35um technology. Post layout simulations indicated a +/-5G dynamic range, a maximum bandwidth of 1.58 kHz, non-linearity of 0.077% and a resolution of 10.5 uG/Hz^0.5. The readout circuit charge amplifier is fully diff…
Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8x8 pixe…
For the need of measurements focused in condensed matter physics and especially Bernoulli effect in superconductors we have developed an active resonator with dual operational amplifiers. A tunable high-Q resonator is performed in the schematics of the the General Impedance Converter (GIC). In the framework of frequency dependent open-loop gain of operational amplifiers, a general formula of the frequency dependence of the impedance of GIC is derived. The explicit formulas for the resonance frequency and Q-factor include as immanent parameter the crossover frequency of the operational amplifie…
Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices int…
We present a thorough theoretical analysis and experimental study of the shot and electronic noise spectra of a balanced optical detector based on an operational amplifier (OA) connected in a transimpedance scheme. We identify and quantify the primary parameters responsible for the limitations of the circuit, in particular the bandwidth and shot-to-electronic noise clearance. We find that the shot noise spectrum can be made consistent with the second order Butterworth filter, while the electronic noise grows linearly with the second power of the frequency. Good agreement between the theory and…
An electrical analysis is performed for a memristor crossbar array integrated with operational amplifiers including the effects of parasitic or contact resistances. It is shown that the memristor crossbar array can act as a transfer matrix for a multiple input-multiple output signal processing system. Special cases of the transfer matrix are described related to reconfigurable analog filters, waveform generators, analog computing, and pattern similarity. Keywords: transfer matrix, memristor, analog electronics, crossbar, operational amplifier, reconfigurable electronics
We describe a dark matter axion detector designed, constructed, and operated both as an innovation platform for new cavity and amplifier technologies and as a data pathfinder in the $5 - 25$ GHz range ($\sim20-100\: μ$eV). The platform is small but flexible to facilitate the development of new microwave cavity and amplifier concepts in an operational environment. The experiment has recently completed its first data production; it is the first microwave cavity axion search to deploy a Josephson parametric amplifier and a dilution refrigerator to achieve near-quantum limited performance.
The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed t…
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplifi…
This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150\,nm CMOS process. DMAPS exploit high voltage and/or high resistivity inclusion of modern CMOS technologies to achieve substantial depletion in the sensing volume. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade in 2025 for the High Luminosity Large Hadron Collider (HL-LHC). This type of devices has a lower production cost and lower materia…
The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of s…
Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prot…
An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purp…
A wide swing charge sensitive amplifier (CSA) has been developed, as a part of a front-end electronics (FEE) readout ASIC, for a prototype silicon tungsten (Si-W) based electromagnetic (EM) calorimeter. The CSA, designed in 0.35 $μ$m N-well CMOS technology using 5V MOS transistors, has a wide linear operating range of 2.6 pC w.r.t the input charge with a power dissipation of 2.3 mW. A noise figure (ENC) of 820 e$^-$ at 0 pF of detector capacitance with a noise slope of 25 e$^-$/pF has been achieved (when followed by a CR-RC$^2$ filter of 1.2 $μ$s peaking time). This design of CSA provides a dy…
A wide-band current preamplifier based on a composite operational amplifier is proposed. It has been shown that the bandwidth of the preamplifier can be significantly increased by enhancing the effective open-loop gain of the composite preamplifier. The described preamplifier with current gain 10$^7$ V/A showed the bandwidth of about 100 kHz with 1 nF input shunt capacitance. The current noise of the amplifier was measured to be about 46 fA/$\sqrt{\rm Hz}$ at 1 kHz, close to the design noise minimum. The voltage noise was found to be about 2.9 nV/$\sqrt{\rm Hz}$ at 1 kHz, which is in a good ag…
This paper presents a low noise amplifier for large arrays of silicon photomultipliers (SiPMs) operated in cryogenic environments, especially liquid argon (87 K) and liquid nitrogen (77 K). The goal is for one amplifier to read out a total photosensitive surface of tens of cm$^2$ while retaining the capability to resolve single photoelectron signals. Due to the large capacitance of SiPMs, typically a few nF per cm$^2$, the main contributor to noise is the series (voltage) component. A silicon-germanium heterojunction bipolar transistor (HBT) was selected as the input device of the cryogenic am…
The photon detection system of the first far detector (FD1-HD) of the DUNE experiment will detect scintillation photons produced by particle interactions in a kiloton-scale liquid Argon time projection chamber. The photon detectors of choice are silicon photomultipliers (SiPM), 6$\times$6 mm$^2$ each, arranged in groups of 48, which present a significantly low impedance to the front-end electronics. This paper details the design of a cryogenic amplifier with exceptionally low white voltage noise of 0.37 nV$\sqrt{Hz}$, based on a silicon-germanium input transistor and a BiCMOS fully differentia…
This paper describes the design and testing results of an 8 channels preamplifier-discriminator circuit based on a resistive feedback Transimpedance Amplifier architecture and a Leading-Edge Discriminator stage for fast high-accuracy time measurement systems. The circuit has been designed in a 130 nm CMOS technology. It is intended to be used as a Front-End-Electronics for measuring the Time Of Flight using diamond detectors. The size of the chip is 1.27x1.22mm2 and the total power consumption of one channel is 1.5mW with a power supply of 1.2V. Testing results shows a timing jitter of about 8…
Influence of Radiation and AC Coupling on Time Performance of Analog Pixels Test Structures in 65 nm CMOS technology
European Organisation for Nuclear Research (CERN)（欧洲核子研究组织）；University of Torino（都灵大学）；INFN, Sezione di Torino（意大利国家核物理研究所都灵分部）；INFN, Sezione di Trieste（意大利国家核物理研究所的里雅斯特分部）；University of Bari（巴里大学）；INFN, Sezione di Bari（意大利国家核物理研究所巴里分部）；Polytechnic of Bari（巴里理工大学）；University of Trieste（的里雅斯特大学）
Two different depleted monolithic CMOS active pixel sensor (DMAPS) prototypes with a fully synchronous column-drain read-out architecture were designed and tested: LF-Monopix and TJ-Monopix. These chips are part of a R&D effort towards a suitable implementation of a CMOS DMAPS for the HL-LHC ATLAS Inner Tracker. LF-Monopix was developed using a 150nm CMOS process on a highly resistive substrate (>2 k$Ω\,$cm), while TJ-Monopix was fabricated using a modified 180 nm CMOS process with a 1 k$Ω\,$cm epi-layer for depletion. The chips differ in their front-end design, biasing scheme, pixel pitch, di…
