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arXiv 2407.18528physics.ins-det
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采用65 nm CMOS成像工艺实现的片内运算放大器模拟像素测试结构的时间性能

Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process

Gianluca Aglieri Rinella, Luca Aglietta, Matias Antonelli, Francesco Barile, Franco Benotto, Stefania Maria Beolè, Elena Botta, Giuseppe Eugenio Bruno, Francesc… 展开作者

Gianluca Aglieri Rinella, Luca Aglietta, Matias Antonelli, Francesco Barile, Franco Benotto, Stefania Maria Beolè, Elena Botta, Giuseppe Eugenio Bruno, Francesca Carnesecchi, Domenico Colella, Angelo Colelli, Giacomo Contin, Giuseppe De Robertis, Florina Dumitrache, Domenico Elia, Chiara Ferrero, Martin Fransen, Alex Kluge, Shyam Kumar, Corentin Lemoine, Francesco Licciulli, Bong-Hwi Lim, Flavio Loddo, Magnus Mager, Davide Marras, Paolo Martinengo, Cosimo Pastore, Rajendra Nath Patra, Stefania Perciballi, Francesco Piro, Francesco Prino, Luciano Ramello, Arianna Grisel Torres Ramos, Felix Reidt, Roberto Russo, Valerio Sarritzu, Umberto Savino, David Schledewitz, Mariia Selina, Serhiy Senyukov, Mario Sitta, Walter Snoeys, Jory Sonneveld, Miljenko Suljic, Triloki Triloki, Andrea Turcato

AI总结:

面向ALICE ITS3升级,研究表征TPSCo 65 nm CMOS APTS-OA像素原型,最佳变体达到63 ps时间分辨率、99%以上探测效率和2 μm空间分辨率。

摘要:

在CERN EP关于单片传感器的研发以及ALICE ITS3升级的背景下,Tower Partners Semiconductor Co(TPSCo)65 nm工艺已通过高能物理应用认证,并被ALICE ITS3升级采用。为详细表征该工艺下的像素性能,研究人员设计了一种模拟像素测试结构(APTS):其面向4×4像素的小矩阵,具备基于运算放大器的快速逐像素缓冲,并采用带有小收集电极和极不均匀电场的传感器。研究使用120 GeV/c正强子束流对该芯片若干具有不同像素设计的变体进行了表征。结果表明,性能最佳的APTS-OA原型变体实现了63 ps的时间分辨率、超过99%的探测效率以及2 μm的空间分辨率,凸显了TPSCo 65 nm CMOS成像技术在高能物理及其他需要精确时间测量、高探测效率和优异空间分辨率领域中的潜力。

英文摘要:

In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high energy physics, and adopted for the ALICE ITS3 upgrade. An Analog Pixel Test Structure (APTS) featuring fast per pixel operational-amplifier-based buffering for a small matrix of four by four pixels, with a sensor with a small collection electrode and a very non-uniform electric field, was designed to allow detailed characterization of the pixel performance in this technology. Several variants of this chip with different pixel designs have been characterized with a (120 GeV/$c$) positive hadron beam. This result indicates that the APTS-OA prototype variants with the best performance achieve a time resolution of 63 ps with a detection efficiency exceeding 99% and a spatial resolution of 2 $μ$m, highlighting the potential of TPSCo 65nm CMOS imaging technology for high-energy physics and other fields requiring precise time measurement, high detection efficiency, and excellent spatial resolution.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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