数字驱动系统中模拟动态的快速FPGA仿真
Fast FPGA emulation of analog dynamics in digitally-driven systems
摘要：
在本文中，我们提出了一个架构的FPGA仿真的混合信号系统，实现高精度，高吞吐量。我们将模块的模拟输出表示为对其模拟输入变化的阶跃响应的叠加，并且仅在数字子系统需要时才对输出进行评估。因此，我们的架构是数字驱动的系统，也就是说，在这些模拟动态块的输入只改变数字时钟沿。我们实现了一个高速链路收发器的设计，使用所提出的架构上Xilinx FPGA。这个设计演示了我们的方法如何打破模拟速率和时间分辨率之间的联系，这是以前的方法的特点。该仿真器非常灵活，允许实时调整模拟动态特性、时钟抖动和各种设计参数。我们证明，我们的架构实现了1%的准确性，同时运行速度比一个相当的高性能CPU模拟快3个数量级。
英文摘要：
In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog input, and the output is evaluated only when needed by the digital subsystem. Our architecture is therefore intended for digitally-driven systems; that is, those in which the inputs of analog dynamical blocks change only on digital clock edges. We implemented a high-speed link transceiver design using the proposed architecture on a Xilinx FPGA. This design demonstrates how our approach breaks the link between simulation rate and time resolution that is characteristic of prior approaches. The emulator is flexible, allowing for the real-time adjustment of analog dynamics, clock jitter, and various design parameters. We demonstrate that our architecture achieves 1% accuracy while running 3 orders of magnitude faster than a comparable high-performance CPU simulation.
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