BRISC-V：一个开源的空间探索体系结构设计工具
BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox
摘要：
在这项工作中，我们介绍了一个用于寄存器传输级（RTL）架构设计空间探索的平台。该平台是一个开源的、参数化的、可综合的RTL模块集，用于设计基于RISC-V的单核和多核架构系统。该平台采用高度模块化设计。它提供了高度参数化的可组合RTL模块，可快速准确地探索基于RISC-V的不同核心复杂性、多级缓存和内存组织、系统拓扑、路由器架构和路由方案。该平台可用于RTL级仿真和基于FPGA的仿真。硬件模块是在可合成的Verilog中实现的，不使用特定于供应商的块。该平台包括一个RISC-V编译器工具链，以帮助开发内核软件，一个基于Web的系统配置图形用户界面（GUI）和一个基于Web的RISC-V组装模拟器。该平台支持多种RISC-V架构，从简单的单周期处理器到具有复杂存储层次结构和片上网络的多核SoC。这些模块旨在支持增量添加和修改。组件之间的接口特别设计为允许修改或替换处理器的部分，例如整个缓存模块、内核或单个流水线级，而不会影响系统的其余部分。该平台允许研究人员使用可合成的RTL快速实例化完整的RISC-V多核系统，并进行有针对性的修改以满足他们的需求。完整的平台（包括Verilog源代码）可以从https://ascslab.org/research/briscv/explorer/explorer.html下载。
英文摘要：
In this work, we introduce a platform for register-transfer level (RTL) architecture design space exploration. The platform is an open-source, parameterized, synthesizable set of RTL modules for designing RISC-V based single and multi-core architecture systems. The platform is designed with a high degree of modularity. It provides highly-parameterized, composable RTL modules for fast and accurate exploration of different RISC-V based core complexities, multi-level caching and memory organizations, system topologies, router architectures, and routing schemes. The platform can be used for both RTL simulation and FPGA based emulation. The hardware modules are implemented in synthesizable Verilog using no vendor-specific blocks. The platform includes a RISC-V compiler toolchain to assist in developing software for the cores, a web-based system configuration graphical user interface (GUI) and a web-based RISC-V assembly simulator. The platform supports a myriad of RISC-V architectures, ranging from a simple single cycle processor to a multi-core SoC with a complex memory hierarchy and a network-on-chip. The modules are designed to support incremental additions and modifications. The interfaces between components are particularly designed to allow parts of the processor such as whole cache modules, cores or individual pipeline stages, to be modified or replaced without impacting the rest of the system. The platform allows researchers to quickly instantiate complete working RISC-V multi-core systems with synthesizable RTL and make targeted modifications to fit their needs. The complete platform (including Verilog source code) can be downloaded at https://ascslab.org/research/briscv/explorer/explorer.html.
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